Method for forming capacitor in semiconductor device
View Patent ↗Upon a deep-hole capacitor fabrication, a hole is formed in an insulator layer, and then a film of a conductive material is formed on the insulator layer and on the whole inner surface of the hole. The film and the insulator layer are exposed to a chemical-mechanical polishing process to form a lower electrodes of the conductive material. A capacitor dielectric on the lower electrode is formed, and then an upper electrode is formed on the capacitor dielectric.
1. A method for forming a capacitor, comprising:
providing a substrate with an insulator layer;
forming a hole in the insulator layer, the hole having an opening, a side surface and a bottom surface, the side surface having a bowing shape in a plane perpendicular to the substrate;
forming a film of a conductive material on the insulator layer and on the side surface and the bottom surface of the hole;
exposing the film and the insulator layer to a chemical-mechanical polishing process to remove the film and the insulator in part in a direction perpendicular to the substrate so as to form a lower electrode of the conductive material and a polished insulator, the polished insulator defining a widened opening larger in size than the opening;
forming a capacitor dielectric on the lower electrode; and
forming an upper electrode on the capacitor dielectric, wherein
forming the hole comprises:
forming a hardmask with a patterned aperture on the insulator layer; and exposing the insulator layer to an anisotropic etch process by using the hardmask, wherein the hardmask is removed by the chemical-mechanical polishing process, and wherein
the exposing the insulator layer to an anisotropic etch process is carried out so that the hole is provided with a particular vase-shaped profile; the particular vase-shaped profile has an upper section extending downwardly from the opening to a predetermined level and a lower section extending downwardly from the predetermined level to the bottom surface; the upper section has larger sizes with increased depths; and the lower section has smaller sizes with increased depths.
2. The method according to claim 1 , wherein the chemical-mechanical polishing process is carried out until the lower electrode and the polished insulator have top surfaces at the predetermined level.
3. The method according to claim 1 , wherein the chemical-mechanical polishing process is carried out until the insulator is removed by a thickness of 200 nm to 300 nm.
4. The method according to claim 1 , wherein the forming a hole is carried out so that the hole has a depth of 2500 nm to 3000 nm.
5. The method according to claim 1 , further comprising: filling the hole at least in part with a protective material before the chemical-mechanical polishing process, and removing the protective material after the chemical-mechanical polishing process.
6. The method according to claim 5 , wherein the protective material is made of photoresist.
7. A method for forming a capacitor, comprising:
providing a substrate with an insulator layer;
forming a hole in the insulator layer, the hole having an opening, a side surface and a bottom surface, the side surface having a bowing shape in a plane perpendicular to the substrate;
forming a film of a conductive material on the insulator layer and on the side surface and the bottom surface of the hole;
exposing the film and the insulator layer to a chemical-mechanical polishing process to remove the film and the insulator in part in a direction perpendicular to the substrate so as to form a lower electrode of the conductive material and a polished insulator, the polished insulator defining a widened opening larger in size than the opening;
filling the hole at least in part with a protective material before the chemical-mechanical polishing process, and removing the protective material after the chemical-mechanical polishing process;
forming a capacitor dielectric on the lower electrode; and
forming an upper electrode on the capacitor dielectric, wherein
the filled protective material has a top surface; and the chemical-mechanical polishing process is finished before top surfaces of the lower electrode and the polished insulator reach the same height as the top surface of the protective material.
8. The method according to claim 5 , wherein the protective material is made of a silicon oxide or another silicon oxide with impurities, whose wet etch rate is equal to or higher than that of the insulator layer in accordance with a particular wet etchant.
9. The method according to claim 8 , wherein the protective material is formed by a chemical vapor deposition or spin coating.
10. A method for forming a capacitor, comprising:
providing a substrate with an insulator layer;
forming a hole in the insulator layer, the hole having an opening, a side surface and a bottom surface, the side surface having a bowing shape in a plane perpendicular to the substrate;
forming a film of a conductive material on the insulator layer and on the side surface and the bottom surface of the hole;
exposing the film and the insulator layer to a chemical-mechanical polishing process to remove the film and the insulator in part in a direction perpendicular to the substrate so as to form a lower electrode of the conductive material and a polished insulator, the polished insulator defining a widened opening larger in size than the opening;
forming a capacitor dielectric on the lower electrode; and
forming an upper electrode on the capacitor dielectric,
the insulator layer comprising a base insulator layer, a mark layer formed on the base insulator layer and an additional insulator layer formed on the mark layer, wherein the mark layer serves as an end level of the chemical-mechanical polishing process.
11. The method according to claim 10 , wherein the additional insulator layer has a thickness of 200 nm to 300 nm.
12. The method according to claim 10 , wherein the protective material is made of photoresist.
13. The method according to claim 7 , wherein the protective material is made of a silicon oxide or another silicon oxide with impurities, whose wet etch rate is equal to or higher than that of the insulator layer in accordance with a particular wet etchant.