Data output circuit of synchronous memory device
View Patent ↗A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function. Each pipelatch comprises a data switching section for switching an output path of N bits data; a first data selection section for receiving one half of the N bits data and outputting the one half in response to a first control signal; a second data selection section for receiving the other half of the N bits data and outputting the other half in response to the first control signal; a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.
1. A data output circuit of a synchronous memory device including a plurality of pipelatches having an N bits prefetch function, each pipelatch comprising:
a data switching section for receiving N bits data and switching an output path of the N bits data depending upon a starting column address applied by a read command and a data output mode;
a first data selection section for receiving one half of the N bits data outputted from the data switching section and sequentially outputting the one half of the N bits data in response to a first control signal;
a second data selection section for receiving the other half of the N bits data outputted from the data switching section which remains by excluding the one half applied to the first data selection section and sequentially outputting the other half of the N bits data in response to the first control signal;
a first shifter for outputting a second control signal delayed by a first time after receiving the first control signal; and
a second shifter for receiving the data outputted from the second data selection section and outputting the data with a delay of the first time in response to the second control signal.
2. The data output circuit as set forth in claim 1 , further comprising:
a pre-driver for receiving the data sequentially outputted from the first data selection section and the data sequentially outputted from the second shifter, wherein the data outputted from the first data selection section and the data outputted from the second shifter are alternately applied to the pre-driver.
3. The data output circuit as set forth in claim 2 , wherein the first time corresponds to a half (½tCK) of a cycle (tCK) of a clock signal applied to the synchronous memory device, and a time at which the data is initially outputted from the second data selection section is earlier by ½tCK than a time at which the data is initially outputted from the first data selection section.
4. The data output circuit as set forth in claim 3 , wherein the first data selection section is composed of a first switching part which is turned on and off by a third control signal and a first buffer of which enabled or disabled state is determined by the first control signal; the second data selection section is composed of a second switching part which is turned on and off by a fourth control signal and a second buffer of which enabled or disabled state is determined by the first control signal; the first and second switching parts receive the data outputted from the data switching section; data having passed through the first switching part is applied to the first buffer; data having passed through the second switching part is applied to the second buffer; an output of the first buffer is an output of the first data selection section; and an output of the second buffer is an output of the second data selection section.
5. The data output circuit as set forth in claim 4 , wherein the plurality of pipelatches commonly use the first control signal.
6. The data output circuit as set forth in claim 2 , wherein the plurality of pipelatches share the pre-driver.