Adaptive play-out buffers and clock operation in packet networks
View Patent ↗Methods and apparatus are described for a play-out buffer. A method includes writing a data packet into a jitter buffer at a write address specified by a write address generator; incrementing the write address generator; generating the difference between the write address and a current read address specified by a read address generator; reading a data packet from the jitter buffer from the current read address specified by the read address generator; generating a new read address based on the difference between the write address and the current read address by the read address generator. An apparatus includes a jitter buffer; a write address generator for storing a write address; a read address generator for storing a current read address; a read address increment control; wherein the read address increment control sets the future read address based on the difference between the write address and the current read address. Another method of driving a numerically controlled oscillator includes providing a local clock with a clock cycle; generating a numerical value during each clock cycle; adding the numerical value to an accumulator having a most significant bit; and using the value of the most significant bit as an oscillator. Another apparatus includes a local clock with a clock cycle; a jitter buffer having a write address and a current read address; a first accumulator; a second accumulator having a most significant bit; an increment control; wherein the increment control sets an accumulation value to be added to the first accumulator based on the difference between the write address and the current read address; wherein the value of the second accumulator depends on the first accumulator; and wherein the most significant bit functions as an oscillator.
1. A method of driving a numerically controlled oscillator comprising:
providing a local clock with a clock cycle;
generating an increment value based on a difference between a write address and a current read address of a jitter buffer;
adding the increment value to a prior frequency value to produce a current frequency value
storing the current frequency value; and
using the most significant bit of the current frequency value as a timing signal.
2. The method of claim 1 , wherein the timing signal is used as a digital-to-analog clock of the receiving end of an electronic communication system.
3. The method of claim 1 , further comprising:
adjusting the current frequency value to be within a predetermined range.
4. A machine readable storage medium, comprising a program for performing the method of claim 1 .
5. The method of claim 1 , further comprising:
providing a timer; and
assigning a threshold value T, wherein the increment value is generated based on the difference Δn between the write address and the current read address of the jitter buffer based on the following criteria: if |Δn|≧T, set the increment value to 0; if T≧|Δn|≧0 and the timer has expired, set the increment value to +1 if Δn>0 and −1 if Δn<0, else set the increment value to 0; if Δn=0, reset the timer and set the increment value to 0.
6. The method of claim 1 , further comprising:
providing a timer; and
assigning two threshold value T 2 and T 1 , where T 2 >T 1 , wherein the increment value is generated based on the difference Δn between the write address and the current read address of the jitter buffer based on the following criteria: if |Δn|≧T 2 , set the increment value to 0; if T 2 ≧|Δn|T 1 , and the timer has expired, set the increment value to +1 if Δn>0 and −1 if Δn<0, else set the increment value to 0; if T 1 ≧|Δn|≧0 and the timer has expired, set the increment value to +2 if Δn>0 and −2 if Δn<0, else set the increment value to 0; if Δn=0, reset the timer and set the increment value to 0.
7. The method of claim 1 , wherein the method is used with a service clock generated by a packet-based network.
8. The method of claim 1 , wherein the method is used with a service clock that is independent of a network clock of a packet-based network and the service clock is transferred over the packet-based network.
9. A method of driving a numerically controlled oscillator comprising:
providing a local clock with a clock cycle;
generating an increment value based on a difference between a write address and a current read address of a utter buffer;
adding the increment value to a prior frequency value to produce a current frequency value
storing the current frequency value; and
using the most significant bit of the current frequency value as an adjustment to an incoming timing signal.
10. The method of claim 9 , further comprising:
adjusting the current frequency value to be within a predetermined range.
11. The method of claim 9 , further comprising:
providing a timer; and
assigning a threshold value T, wherein the increment value is generated based on the difference Δn between the write address and the current read address of the jitter buffer based on the following criteria: if |Δn|≧T, set the increment value to 0; if T≧|Δn|≧0 and the timer has expired, set the increment value to +1 if Δn>0 and −1 if Δn<0, else set the increment value to 0; if Δn=0, reset the timer and set the increment value to 0.
12. The method of claim 9 , further comprising:
providing a timer; and assigning two threshold value T 2 and T 1 , where T 2 >T 1 , wherein the increment value is generated based on the difference Δn between the write address and the current read address of the jitter buffer based on the following criteria: if |Δn|≧T 2 , set the increment value to 0; if T 2 ≧|Δn|≧T 1 , and the timer has expired, set the increment value to +1 if Δn>0 and −1 if Δn<0, else set the increment value to 0; if T 1 ≧|Δn|≧0 and the timer has expired, set the increment value to +2 if Δn>0 and −2 if Δn<0, else set the increment value to 0; if Δn=0, reset the timer and set the increment value to 0.
13. The method of claim 9 , wherein the method is used with a service clock generated by a packet-based network.
14. The method of claim 9 , wherein the method is used with a service clock that is independent of a network clock of a packet-based network and the service clock is transferred over the packet-based network.
15. A method of driving a numerically controlled oscillator comprising:
providing a local clock with a clock cycle;
providing a timer;
providing a jitter buffer having a write address and a current read address;
generating the difference between the write address and a current read address;
assigning a threshold value T;
generating an increment value based on the difference Δn between the write address and the current read address of the jitter buffer based on the following criteria: if |Δn|≧T, set the increment value to 0; if T≧|Δn|≧0 and the timer has expired, set the increment value to +1 if Δn>0 and −1 if Δn<0, else set the increment value to 0; if Δn=0, reset the timer and set the increment value to 0;
adding the increment value to a first accumulator;
clipping the first accumulator value to within a predetermined range;
adding the first accumulator value to a second accumulator; and
using the most significant bit of the second accumulator value as a timing signal.
16. An apparatus comprising:
a local clock with a clock cycle;
an accumulator register;
a jitter buffer that is accessed using a write address and a current read address; and
an increment control unit, wherein the increment control unit sets an increment value that is to be added to a frequency value in the accumulator register, based on a difference between the write address and the current read address of the utter buffer, and wherein the most significant bit of the accumulator register functions as a timing signal.
17. An integrated circuit, comprising the apparatus of claim 16 .
18. A circuit board, comprising the integrated circuit of claim 17 .
19. A computer, comprising the circuit board of claim 18 .
20. A network, comprising the computer of claim 19 .
21. The apparatus of claim 16 , wherein the jitter buffer is a dual-port RAM device.
22. The apparatus of claim 16 , wherein the jitter buffer is organized as a modulo-2N circular buffer.
23. An apparatus comprising:
a local clock with a clock cycle;
an accumulator register;
a utter buffer that is accessed using a write address and a current read address; and
an increment control unit, wherein the increment control unit sets an increment value that is to be added to a frequency value in the accumulator register, based on a difference between the write address and the current read address of the utter buffer, and wherein the most significant bit of the accumulator register functions as an adjustment to an incoming timing signal.
24. An integrated circuit, comprising the apparatus of claim 23 .
25. A circuit board, comprising the integrated circuit of claim 24 .
26. A computer, comprising the circuit board of claim 25 .
27. A network, comprising the computer of claim 26 .
28. The apparatus of claim 23 , wherein the jitter buffer is a dual-port RAM device.
29. The apparatus of claim 23 , wherein the jitter buffer is organized as a modulo-2N circular buffer.