Scalable process and structure of JFET for small and decreasing line widths
A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.
1. A contact substructure for an integrated normally off channel JFET comprising:
a layer of silicon dioxide or other insulator (hereafter oxide layer) formed on an upper surface of a substrate in which the normally off JFET is formed in an active area of semiconductor defined by an area of insulating material in said substrate, said oxide layer having:
a first hole formed above and at least partially aligned with a source region of the JFET and filled with polysilicon to form a source contact;
a second hole formed above and at least partially aligned with a drain region of the JFET and filled with polysilicon to form a drain contact; and
a third hole formed above and at least partially aligned with a gate region of the JFET and filled with polysilicon to form a gate contact; and
a nitride layer formed at least on top of said oxide layer;
wherein:
the polysilicon filling said holes in said oxide layer has a surface that is coplanar with a surface of the nitride layer;
the polysilicon forming said gate contact is doped to a first conductivity type;
the polysilicon forming the source contact is doped to a second conductivity type; and
the polysilicon forming the drain contact is doped to the second conductivity type.
2. The apparatus of claim 1 wherein said insulating material in said substrate defining said active area is Shallow Trench Isolation silicon dioxide, and further comprising a layer of nitride formed on said upper surface of said substrate under said layer of oxide and over said Shallow Trench Isolation silicon dioxide to act as an etch stop to prevent etching of said Shallow Trench Isolation silicon dioxide at the locations of said holes for said source and drain contacts.
3. An integrated normally off JFET comprising:
a substrate having at least a portion thereof made of semiconductor and having a top surface;
a well region formed in said semiconductor portion of said substrate and doped to a first conductivity type;
an insulating material formed in said semiconductor portion of said substrate so as to form an active region in said semiconductor portion of said substrate, said active region comprised of a first conductive region in said well in which the normally off JFET is formed and a second conductive region electrically coupled to said first conductive region to which a back gate or well contact is formed;
a conductive channel region formed in said first conductive region and doped to a second conductivity type;
a conductive gate region formed in said first conductive region and doped to said first conductivity type;
a conductive source region formed in said first conductive region and doped to said second conductivity type;
a conductive drain region formed in said first conductive region and doped to said second conductivity type;
a conductive well contact region formed so as to make electrical contact with said second conductive region;
a layer of insulating material formed on said top surface of said substrate and having:
a first hole formed above and at least partially aligned with the source region of the JFET and filled with polysilicon to form a source contact;
a second hole formed above and at least partially aligned with the drain region of the JFET and filled with polysilicon to form a drain contact; and
a third hole formed above and at least partially aligned with the gate region of the JFET and filled with polysilicon to form a gate contact; and
a nitride layer formed on top of said layer of insulating material;
wherein:
the polysilicon filling said holes in said insulating material has a surface that is coplanar with a surface of the nitride layer;
the polysilicon forming the gate contact is doped to the first conductivity type;
the polysilicon forming the source contact is doped to the second conductivity type; and
the polysilicon forming the drain contact is doped to the second conductivity type.
4. The apparatus of claim 3 further comprising a layer of nitride formed on said top surface of said substrate under said layer of insulating material formed on said top surface of said substrate and over said area of insulating material formed in said substrate to define said active area, and wherein said layer of insulating material formed on said top surface of said substrate being silicon dioxide.
5. An integrated, normally-off Junction Field Effect Transistor (JFET) comprising:
a substrate having at least a portion thereof made of semiconductor and having a top surface;
a well region formed in said semiconductor portion of said substrate and doped to a first conductivity type;
an insulating material formed in said semiconductor portion of said substrate so as to form an active region in said semiconductor portion of said substrate in which the normally-off JFET is formed;
a conductive channel region formed in said active region and doped to a second conductivity type;
a conductive gate region formed in said channel region and doped to said first conductivity type;
a conductive source region formed in said channel region and doped to said second conductivity type;
a conductive drain region formed in said channel region and doped to said second conductivity type;
a layer of insulating material formed on said top surface of said substrate and having:
a first hole formed above and at least partially aligned with the source region of the JFET and filled with polysilicon to form a source contact;
a second hole formed above and at least partially aligned with the drain region of the JFET and filled with polysilicon to form a drain contact; and
a third hole formed above and at least partially aligned with the gate region of the JFET and filled with polysilicon to form a gate contact; and
a nitride layer formed on top of said layer of insulating material so as to not block access to said source, drain and gate regions;
wherein:
the polysilicon forming the gate contact has a surface that is coplanar with a surface of the nitride layer;
the polysilicon forming the source contact has a surface that is coplanar with a surface of the nitride layer; and
the polysilicon forming the drain contact has a surface that is coplanar with a surface of the nitride layer.