Patent Assignment
Reel/Frame 035508/0113
Assignment of Assignor's Interest
Recorded: 2015-04-27
Pages: 23
Assignor
SU VOLTA, INC.
Executed: 2015-03-03
Assignee
MIE FUJITSU SEMICONDUCTOR LIMITED
2000 MIZONO, TADO-CHO, KUWANA, MIE 511-0118, JAPAN
Covered Properties
(146)
Integrated Circuit Using Complementary Junction Field Effect Transistor and Mos Transistor in Silicon and Silicon Alloys
Self Aligned Gate Jfet Structure and Method
Scalable Process and Structure for Jfet for Small and Decreasing Line Widths
Circuit Configurations Having Four Terminal Jfet Devices
Oxide Isolated Metal Silicon-Gate Jfet
Level Shifting Circuit Having Junction Field Effect Transistors
Jfet with Built in Back Gate in Either Soi or Bulk Silicon
Junction Field Effect Transistor Input Buffer Level Shifting Circuit
Semiconductor Device, Design Method and Structure
Method of Producing and Operating a Low Power Junction Field Effect Transistor
System and Method for Detecting Multiple Matches
Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof
Jfet Device with Improved Off-State Leakage Current and Method of Fabrication
Jfet Device with Virtual Source and Drain Link Regions and Method of Fabrication
Method for Applying a Stress Layer to a Semiconductor Device and Device Formed Therefrom
Semiconductor Device Having Strain-Inducing Substrate and Fabrication Methods Thereof
Content Addressable Memory Cell Including a Junction Field Effect Transistor
Image Sensing Cell, Device, Method of Operation, and Method of Manufacture
Semiconductor Device Storage Cell Structure, Method of Operation, and Method of Manufacture
Junction Field Effect Dynamic Random Access Memory Cell and Content Addressable Memory Cell
Semiconductor Device Including a Bias Voltage Generator
Common Data Line Signaling and Method
Switching Circuits and Methods for Programmable Logic Devices
Circuit and Method for Generating Electrical Solitons with Junction Field Effect Transistors
Swapped-Body Ram Architecture
System and Method for Routing Connections
Method to Fabricate Gate Electrodes
Double Gate Jfet with Reduced Area Consumption and Fabrication Method Therefor
Semiconductor Device Having a Fin Structure and Fabrication Method Thereof
System and Method for Routing Connections with Improved Interconnect Thickness
Programmable Switch Circuit and Method, Method of Manufacture, and Devices and Systems Including the Same
Voltage-Level Translator
Patent:
7,750,735 →
Application:
12/171,906 →
Current-Limited Output Buffer
Patent:
7,741,882 →
Application:
12/173,405 →
Semiconductor Device Having Strain-Inducing Substrate and Fabrication Methods Thereof
Patent:
7,605,031 →
Application:
12/178,291 →
Jfet Device with Improved Off-State Leakage Current and Method of Fabrication
Patent:
7,709,311 →
Application:
12/178,404 →
Junction Field Effect Transistor Using a Silicon on Insulator Architecture
Dynamic Random Access Memory Having Junction Field Effect Transistor Cell Access Device
Level-Shifting Circuit with Bipolar Junction Transistor
Patent:
7,688,111 →
Application:
12/195,725 →
Self Aligned Gate Jfet Structure and Method
Integrated Circuit Using Complementary Junction Field Effect Transistor and Mos Transistor in Silicon and Silicon Alloys
Jfet with Built in Back Gate in Either Soi or Bulk Silicon
Method of Forming an Oxide Isolated Metal Silicon-Gate Jfet
Memory Cell Including an Emitter Follower and Emitter Follower Sensing Scheme and Method of Reading Data Therefrom
Patent:
7,843,721 →
Application:
12/284,037 →
Junction Field Effect Transistor (Jfet) Structure Having Top-to-Bottom Gate Tie and Method of Manufacture
Patent:
7,943,971 →
Application:
12/316,944 →
A Method for Manufacturing a Junction Field Effect Transistor Having a Double Gate
Method and Apparatus for Improving Sram Write Operations
Patent:
7,848,130 →
Application:
12/339,584 →
Method and Apparatus for Improving Sram Write Operations
Patent:
7,969,759 →
Application:
12/339,618 →
Advanced Jfet with Reliable Channel Control and Method of Manufacture
Patent:
7,736,962 →
Application:
12/349,747 →
Transistor Providing Different Threshold Voltages and Method of Fabrication Thereof
Semiconductor Device with Multiple Transistors Formed in a Partially Depleted Semiconductor-on-Insulator Substrate
Patent:
7,847,354 →
Application:
12/366,791 →
Method for Providing Temperature Uniformity of Rapid Thermal Annealing
Patent:
8,012,873 →
Application:
12/369,169 →
Semiconductor Device, Design Method and Structure
Semiconductor Device, Design Method and Structure
Integrated Circuit Using Complementary Junction Field Effect Transistor and Mos Transistor in Silicon and Silicon Alloys
Circuit Configurations Having Four Terminal Jfet Devices
Electronic Devices and Systems, and Methods for Making and Using the Same
Circuit Configurations Having Four Terminal Devices
Method for Minimizing Defects in a Semiconductor Substrate Due to Ion Implantation
Method for Reducing Punch-Through in a Transistor Device
Method for Minimizing Defects in a Semiconductor Substrate Due to Ion Implantation
Advanced Transistors with Threshold Voltage Set Dopant Structures
Application:
12/895,785 →
Publication:
US 2011/0079861
Advanced Transistors with Punch Through Suppression
Semiconductor Structure and Method of Fabrication Thereof with Mixed Metal Types
Source/Drain Extension Control for Advanced Transistors
Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof
Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof
Digital Circuits Having Improved Transistors, and Methods Therefor
Patent:
8,461,875 →
Application:
13/030,939 →
Semiconductor Structure with Improved Channel Stack and Method for Fabrication Thereof
Analog Circuits Having Improved Transistors, and Methods Therefor
Circuit Devices and Methods Having Adjustable Transistor Body Bias
Junction Field Effect Transistor Having a Double Gate Structure
Circuits and Methods for Measuring Circuit Elements in an Integrated Circuit Device
Patent:
8,599,623 →
Application:
13/336,434 →
Method for Fabricating Multiple Transistor Devices on a Substrate with Varying Threshold Voltages
Patent:
9,406,567 →
Application:
13/407,527 →
Multiple Transistor Types Formed in a Common Epitaxial Layer by Differential Out-Diffusion from a Doped Underlayer
Patent:
8,629,016 →
Application:
13/459,971 →
Epitaxial Channel Transistors and Die with Diffusion Doped Channels
Application:
13/469,201 →
Semiconductor Structure with Substitutional Boron and Method for Fabrication Thereof
Patent:
8,999,861 →
Application:
13/469,249 →
Monitoring and Measurement of Thin Film Layers
Patent:
8,796,048 →
Application:
13/469,598 →
Integrated Circuit Devices and Methods
Patent:
8,811,068 →
Application:
13/471,353 →
Reducing or Eliminating Pre-Amorphization in Transistor Manufacture
Patent:
8,569,156 →
Application:
13/473,403 →
Method for Substrate Preservation During Transistor Fabrication
Patent:
8,778,786 →
Application:
13/482,394 →
Cmos Gate Stack Structures and Processes
Patent:
8,735,987 →
Application:
13/489,824 →
Electronic Devices and Systems, and Methods for Making and Using the Same
Analog Transistor
Patent:
8,748,270 →
Application:
13/553,902 →
Electronic Device with Controlled Threshold Voltage
Patent:
8,748,986 →
Application:
13/559,554 →
Cmos Structures and Processes Based on Selective Thinning
Patent:
8,614,128 →
Application:
13/591,767 →
Porting a Circuit Design from a First Semiconductor Process to a Second Semiconductor Process
Patent:
8,645,878 →
Application:
13/592,122 →
Semiconductor Structure with Reduced Junction Leakage and Method of Fabrication Thereof
Patent:
8,637,955 →
Application:
13/600,647 →
Electronic Devices and Systems, and Methods for Making and Using the Same
Electronic Devices and Systems, and Methods for Making and Using the Same
Tools and Methods for Yield-Aware Semiconductor Manufacturing Process Target Generation
Patent:
8,713,511 →
Application:
13/621,698 →
Semiconductor Devices with Dopant Migration Suppression and Method of Fabrication Thereof
Patent:
9,112,057 →
Application:
13/622,194 →
Multiple Transistor Types Formed in a Common Epitaxial Layer by Differential Out-Diffusion from a Doped Underlayer
Patent:
8,653,604 →
Application:
13/624,449 →
Analog Circuits Having Improved Insulated Gate Transistors, and Methods Therefor
Patent:
9,236,466 →
Application:
13/646,506 →
Body Bias Circuits and Methods
Patent:
8,816,754 →
Application:
13/668,063 →
Tipless Transistors, Short-Tip Transistors, and Methods and Circuits Therefor
Patent:
8,895,327 →
Application:
13/708,983 →
Memory Circuits and Methods of Making and Designing the Same
Patent:
8,819,603 →
Application:
13/716,080 →
Transistor Having Reduced Junction Leakage and Methods of Forming Thereof
Patent:
8,883,600 →
Application:
13/725,152 →
Circuits and Devices for Generating Bi-Directional Body Bias Voltages, and Methods Therefor
Patent:
8,970,289 →
Application:
13/747,268 →
Process for Manufacture of Integrated Circuits with Different Channel Doping Transistor Architectures and Devices Therefrom
Patent:
8,877,619 →
Application:
13/748,418 →
Integrated Circuits Having a Plurality of High-K Metal Gate FETs with Various Combinations of Channel Foundation Structure and Gate Stack Structure and Methods of Making Same
Patent:
9,093,550 →
Application:
13/755,887 →
Source/Drain Extension Control for Advanced Transistors
Analog Circuits Having Improved Transistors, and Methods Therefor
Sram Cell Layout Structure and Devices Therefrom
Patent:
8,863,064 →
Application:
13/776,917 →
Integrated Circuit Device Methods and Models with Predicted Device Metric Variations
Patent:
9,268,885 →
Application:
13/780,006 →
Multiple Vdd Clock Buffer
Patent:
8,994,415 →
Application:
13/783,167 →
Ring Oscillator with Nmos or Pmos Variation Insensitivity
Patent:
8,988,153 →
Application:
13/792,006 →
Method for Fabricating a Transistor Device with a Tuned Dopant Profile
Patent:
9,299,801 →
Application:
13/828,262 →
Transistor Array Structure
Patent:
9,449,967 →
Application:
13/835,327 →
Integrated Circuit Device Body Bias Circuits and Methods
Patent:
9,112,495 →
Application:
13/838,221 →
Digital Circuits Having Improved Transistors, and Methods Therefor
Patent:
9,184,750 →
Application:
13/891,929 →
Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages
Semiconductor Structure with Improved Channel Stack and Method for Fabrication Thereof
Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof
Sram Performance Monitor
Patent:
8,976,575 →
Application:
14/014,076 →
Deeply Depleted Mos Transistors Having a Screening Layer and Methods Thereof
Source/Drain Extension Control for Advanced Transistors
Reducing or Eliminating Pre-Amorphization in Transistor Manufacture
Semiconductor Structure and Method of Fabrication Thereof with Mixed Metal Types
Dynamic Random Access Memory (Dram) with Low Variation Transistor Peripheral Circuits
Circuits and Methods for Measuring Circuit Elements in an Integrated Circuit Device
Patent:
8,837,230 →
Application:
14/072,761 →
Slew Based Process and Bias Monitors and Related Methods
Patent:
9,093,997 →
Application:
14/081,264 →
Electronic Devices and Systems, and Methods for Making and Using the Same
Cmos Structures and Processes Based on Selective Thinning
Application:
14/101,691 →
Bit Interleaved Low Voltage Static Random Access Memory (Sram) and Related Methods
Patent:
9,070,477 →
Application:
14/104,182 →
Semiconductor Structure with Reduced Junction Leakage and Method of Fabrication Thereof
Integrated Circuit Process and Bias Monitors and Related Methods
Patent:
9,112,484 →
Application:
14/136,258 →
Porting a Circuit Design from a First Semiconductor Process to a Second Semiconductor Process
Patent:
8,806,395 →
Application:
14/171,224 →
Semiconductor Devices Having Fin Structures and Fabrication Methods Thereof
Patent:
9,054,219 →
Application:
14/173,570 →
Multiple Transistor Types Formed in a Common Epitaxial Layer by Differential Out-Diffusion from a Doped Underlayer
Patent:
8,916,937 →
Application:
14/180,888 →
Advanced Transistors with Punch Through Suppression
Source/Drain Extension Control for Advanced Transistors
Cmos Gate Stack Structures and Processes
Patent:
9,281,248 →
Application:
14/266,115 →
Analog Transistor
Buried Channel Deeply Depleted Channel Transistor
Patent:
9,478,571 →
Application:
14/286,063 →
Electronic Device with Controlled Threshold Voltage
Patent:
8,963,249 →
Application:
14/292,806 →
Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof
Porting a Circuit Design from a First Semiconductor Process to a Second Semiconductor Process
Patent:
9,117,746 →
Application:
14/336,793 →
Power Up Body Bias Circuits and Methods
Integrated Circuit Devices and Methods
Patent:
9,362,291 →
Application:
14/455,892 →
Body Bias Circuits and Methods
Patent:
9,154,123 →
Application:
14/463,399 →
Operational Amplifier Input Offset Correction with Transistor Threshold Voltage Adjustment
Circuits and Methods for Measuring Circuit Elements in an Integrated Circuit Device
Patent:
9,297,850 →
Application:
14/487,053 →
Analog Circuits Having Improved Transistors, and Methods Therefor
Sram Cell Layout Structure and Devices Therefrom
Patent:
9,424,385 →
Application:
14/511,487 →
Tipless Transistors, Short-Tip Transistors, and Methods and Circuits Therefor
Patent:
9,385,121 →
Application:
14/533,414 →
High Uniformity Screen and Epitaxial Layers for Cmos Devices
Related Assignments
(23)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Feb 15, 2006
From: KAPOOR, ASHOK K.
To: DSM SOLUTIONS
Reel/Frame 017566/0898 →
Assignment of Assignor's Interest
Jun 13, 2006
From: KAPOOR, ASHOK KUMAR
To: DSM SOLUTIONS, INC.
Reel/Frame 017969/0981 →
Assignment of Assignor's Interest
Jul 28, 2006
From: THUMMALAPALLY, DAMODAR R.; CHOU, RICHARD K.
To: DSM SOLUTIONS, INC.
Reel/Frame 018140/0795 →
Assignment of Assignor's Interest
Sep 1, 2006
From: CHOU, RICHARD K.; THUMMALAPALLY, DAMODAR R.
To: DSM SOLUTIONS, INC.
Reel/Frame 018271/0128 →
Assignment of Assignor's Interest
Oct 12, 2006
From: KAPOOR, ASHOK KUMAR
To: DSM SOLUTIONS, INC., A DELAWARE CORPORATION
Reel/Frame 018392/0875 →
Assignment of Assignor's Interest
Oct 31, 2006
From: VORA, MADHUKAR B.
To: DSM SOLUTIONS, INC.
Reel/Frame 018492/0568 →
Assignment of Assignor's Interest
Nov 14, 2006
From: KAPOOR, ASHOK KUMAR; VORA, MADHUKAR
To: DSM SOLUTIONS, INC., A DELAWARE CORPORATION
Reel/Frame 018526/0905 →
Assignment of Assignor's Interest
Dec 7, 2006
From: KAPOOR, ASHOK KUMAR
To: DSM SOLUTIONS, INC.
Reel/Frame 018671/0276 →
Assignment of Assignor's Interest
Mar 29, 2007
From: THUMMALAPALLY, DAMODAR R.
To: DSM SOLUTIONS, INC.
Reel/Frame 019087/0538 →
Assignment of Assignor's Interest
May 1, 2007
From: THUMMALAPALLY, DAMODAR R.
To: DSM SOLUTIONS, INC.
Reel/Frame 019313/0074 →
Assignment of Assignor's Interest
May 3, 2007
From: MIN, SUNG-KI
To: DSM SOLUTIONS, INC.
Reel/Frame 019244/0969 →
Assignment of Assignor's Interest
May 3, 2007
From: SAHA, SAMAR K.; KAPOOR, ASHOK K.
To: DSM SOLUTIONS, INC.
Reel/Frame 019245/0655 →
Assignment of Assignor's Interest
May 3, 2007
From: SAHA, SAMAR K.; KAPOOR, ASHOK K.
To: DSM SOLUTIONS, INC.
Reel/Frame 019245/0461 →
Assignment of Assignor's Interest
May 4, 2007
From: KAPOOR, ASHOK K.
To: DSM SOLUTIONS, INC.
Reel/Frame 019251/0511 →
Assignment of Assignor's Interest
May 4, 2007
From: KAPOOR, ASHOK K.
To: DSM SOLUTIONS, INC.
Reel/Frame 019251/0642 →
Assignment of Assignor's Interest
May 8, 2007
From: VORA, MADHUKAR; KAPOOR, ASHOK KUMAR
To: DSM SOLUTIONS, INC.
Reel/Frame 019266/0007 →
Corrective Assignment to Correct the Serial Number Number, Previously Recorded on Reel 018526 Frame 0905.
Sep 10, 2007
From: KAPOOR, ASHOK KUMAR
To: DSM SOLUTIONS, INC., A DELAWARE CORPORATION
Reel/Frame 019812/0967 →
Corrective Assignment
Sep 14, 2007
From: VORA, MADHUKER; KAPOOR, ASHOK KUMAR
To: DSM SOLUTIONS, INC.
Reel/Frame 019883/0494 →
Corrective Coversheet to Correct Docket Number That Was Previously Recorded on Reel 018392, Frame 0875.
Sep 25, 2007
From: VORA, MADHUKAR; KAPOOR, ASHOK KUMAR
To: DSM SOLUTIONS, INC.
Reel/Frame 019873/0910 →
Assignment of Assignor's Interest
Oct 9, 2007
From: VORA, MADHUKAR
To: DSM SOLUTIONS, INC
Reel/Frame 019933/0373 →
Change of Name
Dec 29, 2009
From: DSM SOLUTIONS, INC.
To: SUVOLTA, INC.
Reel/Frame 023708/0505 →
Change of Name
Jan 6, 2010
From: DSM SOLUTIONS, INC.
To: SUVOLTA, INC.
Reel/Frame 023731/0988 →
Change of Name
Feb 19, 2010
From: DSM SOLUTIONS, INC.
To: SUVOLTA, INC.
Reel/Frame 023960/0924 →