Method for applying a stress layer to a semiconductor device and device formed therefrom
A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region.
1. A semiconductor device, comprising:
a substrate formed of semiconductor material;
a source region formed in the substrate and doped with a first type of impurities;
a drain region formed in the substrate and doped with the first type of impurities, the drain region spaced apart from the source region;
a conducting region formed between the source region and the drain region and doped with the first type of impurities, the conducting region operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state;
a channel region formed in the conducting region;
a gate region formed in the substrate and doped with a second type of impurities, the gate region abutting the channel region; and
a stress layer deposited on at least a portion of the conducting region, wherein the stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region;
the semiconductor device comprises a junction field effect transistor (JFET).
2. The semiconductor device of claim 1 , wherein:
the stress layer comprises a first material having a first thermal expansion coefficient;
the conducting region comprises a second material having a second thermal expansion coefficient, and
the first thermal expansion coefficient is greater than the second thermal expansion coefficient.
3. The semiconductor device of claim 2 , wherein the stress layer applies a tensile stress to the conducting region.
4. The semiconductor device of claim 1 , wherein:
the stress layer comprises a first material having a first thermal expansion coefficient;
the conducting region comprises a second material having a second thermal expansion coefficient, and
the first thermal expansion coefficient is less than the second thermal expansion coefficient.
5. The semiconductor device of claim 1 , wherein:
the stress layer comprises a first portion and a second portion;
the first portion of the stress layer is deposited on a first portion of the conducting region and applies a first force to the conducting region; and
the second portion of the stress layer is deposited on a second portion of the conducting region and applies a second force to the conducting region in an opposite direction to the first force.
6. The semiconductor device of claim 5 , wherein the stress layer applies a compressive stress to the conducting region.
7. The semiconductor device of claim 1 , wherein the stress layer comprises silicon nitride.
8. The semiconductor device of claim 1 , further comprising:
a first polysilicon region in ohmic contact with the source region;
a second polysilicon region in ohmic contact with the gate region;
a third polysilicon region in ohmic contact with the drain region, and wherein the stress layer comprises a first portion deposited between the first polysilicon region and the second polysilicon region and a second portion deposited between the second polysilicon region and the third polysilicon region.
9. The semiconductor device of claim 1 , further comprising a gate electrode region which overlays the semiconductor substrate, and a gate contact formed on the gate electrode region and in ohmic contact with the gate region.
10. The semiconductor device of claim 1 , wherein the stress applied to the conducting region, increasing the mobility of charge carriers in at least a portion of the conducting region.
11. A method for creating a stress within a semiconductor device, comprising:
forming a source region doped with a first type of impurities in a semiconductor substrate;
forming a drain region doped with the first type of impurities in the semiconductor substrate, the drain region spaced apart from the source region;
forming a conducting region between the source region and the drain region the conducting region doped with the first type of impurities and operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state;
forming a channel region within the conducting region;
forming a gate region doped with a second type of impurities, the gate region abutting the channel region; and
depositing a stress layer on at least a portion of the conducting region that applies a stress to the conducting region along a boundary of the conducting region, wherein the stress strains at least a portion of the conducting region;
the semiconductor device comprises a junction field effect transistor (JFET).
12. The method of claim 11 , wherein:
the stress layer comprises a first material having a first thermal expansion coefficient;
the conducting region comprises a second material having a second thermal expansion coefficient, and
the first thermal expansion coefficient is greater than the second thermal expansion coefficient.
13. The method of claim 12 , wherein the stress layer applies a tensile stress to the conducting region.
14. The method of claim 11 , wherein:
the stress layer comprises a first material having a first thermal expansion coefficient;
the conducting region comprises a second material having a second thermal expansion coefficient, and
the first thermal expansion coefficient is less than the second thermal expansion coefficient.
15. The method of claim 14 , wherein the stress layer applies a compressive stress to the conducting region.
16. The method of claim 11 , wherein depositing the stress layer comprises:
depositing a first portion of the stress layer on a first portion of the conducting region, wherein the first portion of the stress layer applies a first force to the conducting region; and
depositing a second portion of the stress layer on a second portion of the conducting region, wherein the second portion of the stress layer applies a second force to the conducting region in an opposite direction to the first force.
17. The method of claim 11 , wherein the stress layer comprises silicon nitride.
18. The method of claim 11 , further comprising:
forming a first polysilicon region in ohmic contact with the source region;
forming a second polysilicon region in ohmic contact with the gate region;
forming a third polysilicon region in ohmic contact with the drain region, and wherein depositing the stress layer comprises;
depositing a first portion of the stress layer between the first polysilicon region and the second polysilicon region; and
depositing a second portion of the stress layer between the second polysilicon region and the third polysilicon region.
19. The method of claim 11 , wherein the stress applied to the conducting region, increasing the mobility of charge carriers in at least a portion of the conducting region.
20. The method of claim 11 , further comprising:
forming a gate electrode region overlaying the semiconductor substrate; and
forming a gate contact on the gate electrode region and in ohmic contact with the gate region.