Method and apparatus for improving SRAM write operations
A memory cell includes a first access transistor, first and second pull-up transistors, a depletion transistor, and first and second pull-down transistors. The first access transistor is connected to a word line and connected between a first bit line and a first data node. The first pull-up transistor is connected to a first power supply point and the second pull-up transistor is connected to the first power supply point and the second data node. The first pull-down transistor is connected to a second power supply point and to the first data node and the second pull-down transistor is connected to the depletion transistor and to the second data node. The depletion transistor is connected to the word line and to the second power supply point.
1. A memory cell, comprising:
one or more storage units operable to store one or more data bits;
one or more access units operable to provide a word line or a bit line access to one or more storage units;
wherein the word line is coupled to the storage unit and is operable to control a transistor within the storage unit during one or more write operations; and
wherein enabling the word line during a write operation comprises placing a voltage of approximately 0.5 volts on the word line.