Advanced JFET with reliable channel control and method of manufacture

1. A method for fabricating a junction field effect transistor having an insulating layer formed in a substrate, the method comprising:

forming a silicon layer on the insulating layer, the silicon layer having a first conductivity type and comprising a source region, a drain region, and a channel region;

masking the silicon layer to expose a portion of the channel region in a defined window;

etching at least a portion of the insulating layer under the channel region within the defined window;

depositing a nitride layer on the silicon layer to mask the source region and the drain region and to expose at least a portion of the channel region;

oxidizing at least a portion of the silicon in the exposed channel region to produce silicon dioxide, wherein the silicon dioxide surrounds the silicon of the channel region;

removing the silicon dioxide around the silicon of the channel region; and

forming a gate region that surrounds the silicon of the channel region.

2. The method of claim 1 , further comprising:

depositing oxide on sidewalls of at least a portion of the gate region;

forming separate regions of silicide on each of the source region, the gate region, and the drain region;

depositing an interlayer dielectric material over the transistor;

forming a first contact hole through the interlayer dielectric material to reach the silicide over the source region;

forming a second contact hole through the interlayer dielectric to reach the silicide over the drain region; and

filling the first and second contact holes with metal to form a first metal contact region in ohmic contact with the source region and a second metal contact region in ohmic contact with the drain region.

3. The method of claim 1 , wherein forming the gate region comprises:

depositing polysilicon to surround the silicon of the channel region;

doping the polysilicon a second conductivity; and

etching the polysilicon to define the gate region.

4. The method of claim 1 , wherein etching the insulating layer is performed using an isotropic etch.

5. The method of claim 1 , wherein the insulating layer comprises silicon dioxide.

6. The method of claim 1 , wherein oxidizing the silicon in the exposed channel region comprises performing a thermal oxidation process to consume a portion of the silicon in the channel region.

7. The method of claim 6 , wherein the thermal oxidation process is performed at a predetermined temperature and for a predetermined amount of time to consume a predetermined amount of silicon in the channel region.

8. The method of claim 6 , wherein:

the silicon in the channel region is approximately 60-80 nm thick prior to the thermal oxidation;

the thermal oxidation of the silicon in the channel region is performed at 800° C. for ninety minutes.

9. The method of claim 2 , wherein forming the silicide comprises:

depositing a layer of metal on the source region, the gate region, and the drain region;

thermally reacting the metal with the silicon of the source region and the drain region, and with the polysilicon of the gate region.

10. The method of claim 9 , wherein the metal comprises at least one of cobalt, nickel, titanium, and molybdenum.

11. The method of claim 1 , wherein the first conductivity type comprises n-type and the second conductivity type comprises p-type.

12. The method of claim 1 , wherein the first conductivity type comprises p-type and the second conductivity type comprises n-type.

13. A junction field effect transistor, comprising:

an insulating layer formed in a substrate;

a source region of a first conductivity type formed on the insulating layer;

a layer of silicide on the source region;

a drain region of the first conductivity type formed on the insulating layer and spaced apart from the drain region;

a layer of silicide on the drain region;

a channel region of the first conductivity type which is located between the source region and the drain region and formed on the insulating layer, wherein the channel region has a width that ranges from 5-20 nm and a depth that ranges from 5-20 nm;

a gate region of the second conductivity type surrounding all surfaces of a length of the channel region such that the channel region is embedded within the gate region;

a layer of silicide on the gate region;

a first metal contact region in ohmic contact with the layer of silicide on the source region; and

a second metal contact region in ohmic contact with the layer of silicide on the drain region.

14. A junction field effect transistor, comprising:

an insulating layer formed in a substrate;

a source region of a first conductivity type formed on the insulating layer;

a drain region of the first conductivity type formed on the insulating layer and spaced apart from the drain region;

a channel region of the first conductivity type which is located between the source region and the drain region and formed on the insulating layer;

a gate region of the second conductivity type surrounding all surfaces of a length of the channel region such that the channel region is embedded within the gate region;

a first metal contact region in ohmic contact with a layer of silicide on the source region; and

a second metal contact region in ohmic contact with a layer of silicide on the drain region.

15. The JFET of claim 14 , wherein the first conductivity type comprises n-type and the second conductivity type comprises p-type.

16. The JFET of claim 14 , wherein the first conductivity type comprises p-type and the second conductivity type comprises n-type.

17. The JFET of claim 14 , wherein the channel region has a depth that ranges from 5-20 nm.

18. The JFET of claim 14 , wherein the channel region has a width that ranges from 5-20 nm.

19. The JFET of claim 14 , wherein the insulating layer comprises silicon dioxide.