JFET device with improved off-state leakage current and method of fabrication
A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region of the first conductivity type is formed between the first and second impurity regions. A gate region of a second conductivity type is formed in the substrate between the first and second impurity regions. A gap region is formed in the substrate between the gate region and the first impurity region such that the first impurity region is spaced apart from the gate region.
1. A junction field effect transistor, comprising:
a semiconductor substrate;
a first impurity region of a first conductivity type which is formed in the substrate;
a second impurity region of the first conductivity type which is formed in the substrate and spaced apart from the first impurity region;
a channel region of the first conductivity type which is formed between the first and second impurity regions;
a gate region of a second conductivity type formed in the substrate between the first and second impurity regions;
a first link region of the first conductivity type formed in the substrate between the first impurity region and the gate region, wherein the first link region has a different junction profile than the first impurity region; and
a gap region formed in the substrate between the gate region and the first link region such that the first link region is spaced apart from the gate region, wherein the gap region has a lower doping concentration than the channel region and the first impurity region.
2. The junction field effect transistor of claim 1 , wherein:
the first impurity region comprises a source region; and
the second impurity region comprises a drain region.
3. The junction field effect transistor of claim 1 , further comprising a second link region of the first conductivity type formed in the substrate between the second impurity region and the gate region, wherein the second link region has a different junction profile than the second impurity region.
4. The junction field effect transistor of claim 1 , wherein:
the first impurity region comprises a drain region; and
the second impurity region comprises a source region.
5. The junction field effect transistor of claim 1 , wherein:
the first conductivity type comprises n-type; and
the second conductivity type comprises p-type.
6. The junction field effect transistor of claim 1 , wherein:
the first conductivity type comprises p-type; and
the second conductivity type comprises n-type.
7. The junction field effect transistor of claim 1 , wherein the junction of the first impurity region penetrates deeper into the substrate than the junction of the first link region.
8. The junction field effect transistor of claim 3 , wherein the second link region is spaced apart from the gate region by a distance of between 10 nm to 50 nm.
9. The junction field effect transistor of claim 1 , wherein the first link region is spaced apart from the gate region by a distance of between 10 nm to 50 nm.
10. The junction field effect transistor of claim 1 , further comprising:
a gate electrode region of a second conductivity type which overlays the semiconductor substrate; and
a gate contact region formed on the gate electrode region and in ohmic contact with the gate region.
11. The junction field effect transistor of claim 3 , wherein the gap region comprises a first gap region and further comprising a second gap region formed in the substrate between the gate region and the second link region such that the second link region is spaced apart from the gate region.
12. The junction field effect transistor of claim 11 wherein the second gap region has a lower doping concentration than the channel region and the second impurity region.
13. A junction field effect transistor, comprising:
a semiconductor substrate;
a first impurity region of a first conductivity type which is formed in the substrate;
a second impurity region of the first conductivity type which is formed in the substrate and spaced apart from the first impurity region;
a channel region of the first conductivity type which is formed between the first and second impurity regions;
a gate region of a second conductivity type formed in the substrate between the first and second impurity regions;
a first link region of the first conductivity type formed in the substrate between the first impurity region and the gate region, wherein the first link region has a different junction profile than the first impurity region;
a second link region of the first conductivity type formed in the substrate between the second impurity region and the gate region, wherein the second link region has a different junction profile than the second impurity region;
a first gap region formed in the substrate between the gate region and the first link region such that the first link region is spaced apart from the gate region, wherein the first gap region has a lower doping concentration than the channel region and the first impurity region; and
a second gap region formed in the substrate between the gate region and the second link region such that the second link region is spaced apart from the gate region, wherein the second gap region has a lower doping concentration than the channel region and the second impurity region.
14. The junction field effect transistor of claim 13 , wherein:
the first impurity region comprises a source region; and
the second impurity region comprises a drain region.
15. The junction field effect transistor of claim 13 , wherein the junction of the first impurity region penetrates deeper into the substrate than the junction of the first link region.
16. The junction field effect transistor of claim 13 , wherein:
the first impurity region comprises a drain region; and
the second impurity region comprises a source region.
17. The junction field effect transistor of claim 13 , wherein the first link region is spaced apart from the gate region by a distance of between 10 nm to 50 nm.
18. The junction field effect transistor of claim 13 , wherein:
the first conductivity type comprises n-type; and
the second conductivity type comprises p-type.
19. The junction field effect transistor of claim 13 , wherein:
the first conductivity type comprises p-type; and
the second conductivity type comprises n-type.
20. The junction field effect transistor of claim 13 , wherein the second link region is spaced apart from the gate region by a distance of between 10 nm to 50 nm.
21. The junction field effect transistor of claim 13 , further comprising:
a gate electrode region of a second conductivity type which overlays the semiconductor substrate; and
a gate contact region formed on the gate electrode region and in ohmic contact with the gate region.