Method for minimizing defects in a semiconductor substrate due to ion implantation
Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal.
1. A method for minimizing defects in a semiconductor substrate due to ion implantation, comprising:
providing a semiconductor substrate;
forming a first oxide layer on the entire surface of the semiconductor substrate;
forming a first implant region through the first oxide layer in the semiconductor substrate;
removing the first oxide layer;
forming a second oxide layer on the entire surface of the semiconductor substrate and over the first implant region, wherein the first and second oxide layers are native oxide layers;
forming a second implant region through the second oxide layer in the semiconductor substrate;
subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate;
subjecting the semiconductor substrate to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate, the first anneal being at a lower temperature and longer duration than the second anneal.
2. The method of claim 1 , further comprising:
removing the second oxide layer.
3. The method of claim 2 , wherein the first and second oxide layers are removed by performing a hydrofluoric acid clean and rinse.
4. The method of claim 1 , further comprising:
forming a blanket epitaxial layer on the entire surface of the semiconductor substrate and over the first and second implant regions.
5. The method of claim 4 , wherein the epitaxial layer is formed following the first and second anneals.
6. The method of claim 1 , wherein the first anneal is performed at a temperature of 650° C. for a duration of 150 seconds.
7. The method of claim 6 , wherein the second anneal is performed at a temperature of approximately 1000° C. for a duration of 5 seconds or less.
8. The method of claim 1 , wherein the first anneal is performed at a temperature between 575° C. and 650° C. for a duration between 600 and 150 seconds respectively.
9. The method of claim 8 , wherein the second anneal is performed at a temperature of approximately 1000° C. for a duration of 5 seconds or less.
10. The method of claim 1 , wherein the second anneal is performed at a temperature of approximately 1000° C. for a duration of 5 seconds or less.
11. The method of claim 1 , wherein the semiconductor substrate is a 300 mm wafer and the steps are performed for a 90 nm or less CMOS technology process.
12. The method of claim 1 , wherein the first and second oxide layers are formed by dipping the semiconductor substrate in a chemical wet bath.
13. The method of claim 12 , wherein the chemical wet bath includes hydrogen peroxide or nitric acid.
14. The method of claim 12 , wherein the chemical wet bath includes a solution of hydrochloric acid, hydrogen peroxide, and water.
15. The method of claim 14 , wherein the solution is made up of 1 part hydrochloric acid, 2 parts hydrogen peroxide, and 110 parts water.
16. The method of claim 12 , wherein the semiconductor substrate is dipped in the chemical wet bath for a period of 5 to 20 minutes at a temperature of 25° C. to 70° C.
17. The method of claim 1 , further comprising:
performing a hydrofluoric acid clean and rinse prior to forming the first oxide layer.