Tipless transistors, short-tip transistors, and methods and circuits therefor

1. An integrated circuit, comprising:

a plurality of first transistors having controllable source-drain current paths coupled between a first and second node, the first transistors having a source drain doping profile with extension regions that extend in a lateral direction under a gate electrode of the first transistors, the first transistors configured to selectively couple a first output node to the first or second node in response to one or more input signals, the first transistors being formed in a substrate and having drawn gate lengths of less than one micron; and

at least one tipless transistor formed in the substrate and having a source-drain current path coupled between the first node and the second node, the tipless transistor having a source drain vertical doping profile without extension regions that extend in a lateral direction under a gate electrode of the tipless transistor, the tipless transistor being configured to selectively couple a second output node to the first or second node in response to the one or more input signals, the tipless transistor having a drawn gate length of less than one micron.

2. The integrated circuit of claim 1 , wherein:

at least one first transistor comprises a deeply depleted channel (DDC) transistor having a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the second conductivity type formed below the channel region.

3. The integrated circuit of claim 1 , wherein:

the at least one tipless transistor comprises a deeply depleted channel (DDC) transistor having a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the second conductivity type formed below the channel region.

4. The integrated circuit of claim 1 , wherein:

the at least one tipless transistor is a conventional MOSFET having a source drain vertical doping profile without extension regions that extend in a lateral direction under a gate electrode of the tipless transistor.

5. The integrated circuit of claim 1 , further including:

a delay circuit configured to delay an electrical signal and comprising at least one tipless transistor.

6. The integrated circuit of claim 5 , further including:

a logic gate configured to logically combine signals at a plurality of gate inputs to generate a gate output signal; and

the delay circuit is coupled to a first gate input of the logic gate.

7. The integrated circuit of claim 6 , further including:

a pulse generator that includes

the logic gate having a second gate input coupled to receive an input signal, and

the delay circuit is coupled to receive the input signal and has a delay circuit output coupled to the first gate input.

8. The integrated circuit of claim 7 , wherein:

the pulse generator further includes the logic gate having a third gate coupled to receive an enable signal that enables and disables the pulse generator circuit.

9. The integrated circuit of claim 5 , further including:

a flip-flop circuit comprising

a plurality of latches arranged in series, each latch having a clocked input,

passgates coupled in parallel to an input of the flip-flop circuit, and

the delay circuit is coupled to an input of one of the passgates.

10. The integrated circuit of claim 5 , further including:

a memory cell array;

sense amplifier circuits coupled to the memory cell array and configured to sense data values from memory cells of the memory cell array, the sense amplifier circuits being enabled in response to a sense amplifier control signal;

a control circuit configured to generate an initial sense amplifier control signal; and

the delay circuit is configured to delay the initial sense amplifier control signal to generate the sense amplifier control signal.

11. The integrated circuit of claim 5 , further including:

a timing control circuit configured to generate a periodic timing clock for the integrated circuit, and comprising the delay circuit; wherein

the timing control circuit is selected from the group of: a phase locked loop circuit and a delay locked loop circuit.

12. The integrated circuit of claim 1 , wherein:

the plurality of first transistors have drawn gate lengths of less than 0.5 micron; and

the at least one tipless transistor has a drawn gate length of less than 0.5 micron.

13. An integrated circuit device, comprising:

minimum feature size transistors having gate lengths of less than one micron;

a signal driving circuit comprising

a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node; and

a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor; wherein

at least one of the first or second transistor is a tipless transistor having source and drain vertical doping profiles without extension regions that extend in a lateral direction under a gate electrode, and wherein the first and second transistor are formed in a same integrated circuit substrate.

14. The integrated circuit device of claim 13 , further including:

a latch circuit comprising a feedback path to reinforce a data value at a storage node; wherein

the feedback path includes the signal driving circuit.

15. The integrated circuit device of claim 14 , wherein:

the feedback path is selected from the group of: the driving circuit in series with at least one other inverter; and a latching transistor having a source-drain path coupled between the storage node and one of the first or second power supply nodes, and a gate coupled to an output of the driving circuit.

16. The integrated circuit device of claim 14 , wherein:

the latch circuit is a logic latching circuit that further includes

a logic input section, comprising

a first logic transistor of a first conductivity type having a source-drain path coupled between the storage node and one of a first or second power supply nodes, and

a plurality of second logic transistors having source-drain paths arranged in series between the storage node and the other of the first or second power supply nodes.

17. The integrated circuit device of claim 16 , wherein:

the logic input section includes a clock circuit coupled to a gate of the first logic transistor and a gate of one of the second transistor.

18. The integrated circuit device of claim 16 , further including:

a deeply depleted channel (DDC) transistor having a source and drain doped to a one conductivity type, a substantially undoped channel region, and a highly doped screening region of another conductivity type formed below the channel region; wherein

the DDC transistor is included in any of the group of: the minimum feature size transistors, the first transistor, and the second transistor.

19. The integrated circuit device of claim 13 , wherein:

at least one of the first or second transistor is a short tip transistor having source and drain vertical doping profiles with short extension regions that extend in a lateral direction under a gate electrode, the length of the short extension regions in the lateral direction being less than the corresponding length of the extension regions of one or more other transistors in the integrated circuit.