Transistor having reduced junction leakage and methods of forming thereof
A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.
1. A method for fabricating a transistor with reduced junction leakage current, comprising:
forming a layered stack, the layered stack including at least a doped screening layer and an undoped channel layer over the screening layer;
forming a gate stack over the undoped channel layer;
forming a first spacer on each sidewall of the gate stack;
implanting a shallow lightly doped drain region in the channel on either side of the gate stack and extending a defined distance inward from the outer edges of the gate stack;
implanting deep lightly doped drain regions on either side of the gate stack to vertically extend the shallow lightly doped drain region a selected distance, the deep lightly doped drain region extending no more deeply than the bottom of the screening layer;
forming a second spacer on the first spacer;
implanting a source region on one side of the gate stack and a drain region on another side of the gate stack.
2. The method of claim 1 , wherein the dual lightly doped drain regions are formed with Arsenic.
3. The method of claim 2 , wherein the dual lightly doped drain regions are implanted at a dose in a range of 5×10 13 atoms/cm 2 to 1.5×10 14 atoms/cm 2 and an energy in a range of 10 to 14 keV.
4. The method of claim 1 , further comprising:
implanting a grading layer at substantially a depth of the screening layer.
5. The method of claim 4 , wherein the grading layer is implanted with Phosphorous.
6. The method of claim 5 , wherein the Phosphorous is implanted at a dose in a range of 7×10 13 atoms/cm 2 to 2×10 14 atoms/cm 2 and an energy in a range of 12 to 15 keV.
7. The method of claim 1 , further comprising:
forming an intermediate spacer on the first spacer prior to implanting the dual lightly doped drain regions.
8. The method of claim 7 , wherein the second spacer is formed on the intermediate spacer.
9. The method of claim 7 , further comprising:
etching back the intermediate spacer.
10. The method of claim 9 , wherein the first spacer has a thickness of approximately 6 nanometers and the second spacer has a thickness of approximately 19 nanometers.
11. The method of claim 7 , wherein the first spacer has a thickness of approximately 6 nanometers and the intermediate spacer has a thickness between 0 and 19 nanometers.
12. The method of claim 11 , wherein the second spacer has a thickness such that the total thickness of the first, intermediate, and second spacers is approximately 25 nanometers.
13. The method of claim 1 , further comprising:
implanting a first compensation layer at a depth below the source region and a second compensation layer at a depth below the drain region, the first and second compensation layers being substantially aligned with the dimensions of the source and drain regions.