Voltage-level translator

1. A voltage-level translator, comprising:

an input node operable to receive an input signal associated with an input voltage range;

a differential amplifier operable to:

produce a first voltage swing at a first amplifier node based at least in part on a difference between the input signal and a voltage supply; and

produce a second voltage swing at a second amplifier node based at least in part on a difference between the input signal and the voltage supply, whereby the second voltage swing is less than the first voltage swing;

a first output transistor of a first conductivity type having a drain terminal coupled to an output node and a source terminal coupled to the voltage supply, and operable to provide a substantially constant current to the output node through the drain terminal of the first output transistor;

a second output transistor of a second conductivity type having a drain terminal coupled to the output node, a source terminal coupled to a ground node, and a gate terminal coupled to the second amplifier node, and wherein the second voltage swing produced by the differential amplifier is less than a cut-in voltage of the second output transistor;

a current source operable to provide a substantially constant current to the differential amplifier, and further operable to provide a substantially constant current through the first output transistor;

wherein the voltage-level translator is operable to output a first voltage in an output voltage range at the output node when the input signal is at a high voltage in the input voltage range, and wherein the voltage-level translator is further operable to output a second voltage in the output voltage range at the output node when the input signal is at a low voltage in the input voltage range.

2. The voltage-level translator of claim 1 , wherein the output voltage range is smaller than the input voltage range.

3. The voltage-level translator of claim 2 , wherein the output voltage range is 0 to 0.5 volts.

4. The differential amplifier of claim 1 , wherein the differential amplifier comprises:

a first transistor of a first conductivity type having a source terminal coupled to the current source, a gate terminal coupled to the input node, and a drain terminal coupled to a drain terminal of a second transistor of a second conductivity type;

the second transistor having a source terminal coupled to ground, a gate terminal coupled to a gate terminal of a third transistor of a second conductivity type and to the drain terminal of the first transistor, and a drain terminal coupled to the drain terminal of the first transistor;

the third transistor having a gate terminal coupled to the gate terminal of the second transistor, a source terminal coupled to ground, and a drain terminal coupled to a drain terminal of a fourth transistor of a first conductivity type; and

the fourth transistor having a drain terminal coupled to a drain terminal of the third transistor, a source terminal coupled to the current source, and a gate terminal coupled to a reference voltage supply.

5. The voltage-level translator of claim 1 , wherein the current source comprises a current mirror.

6. The voltage-level translator of claim 1 , wherein at least one of the first output transistor and the second output transistor comprises a junction field effect transistor (JFET).

7. The voltage-level translator of claim 6 , wherein the first output transistor comprises a p-type JFET and the second output transistor comprises an n-type JFET.