Memory cell including an emitter follower and emitter follower sensing scheme and method of reading data therefrom
A memory device including a static random access memory (SRAM) cell comprising junction field effect transistors (JFETs) has been disclosed. The memory cell includes a first bipolar junction transistor (BJT) for driving a bit line at logic levels having a potential outside the potential range in which the SRAM cell operates. An amplifier including a level translator circuit provides a level shifting operation on the data provided by the bit line to provide level shifted data having a voltage swing within the potential range in which the SRAM cell operates. The level translator circuit includes a second BJT. In this way, fast read operation of a SRAM cell comprising JFETs may be provided.
1. A method of reading data from a memory cell including a plurality of junction field effect transistors (JFETs) including the steps of:
receiving data latched by the plurality of JFETs at a base terminal of a first bipolar junction transistor (BJT), the data having a first logic level at a first potential and a second logic level at a second potential; and
providing a data signal at an emitter terminal of the BJT having the first logic level at a third potential and the second logic level at a fourth potential, the third and fourth potentials being outside the first and second potentials.
2. The method of claim 1 , further including the step of:
level translating the data signal so that the first logic level and the second logic levels are within the first potential and the second potential.