Circuit and method for generating electrical solutions with junction field effect transistors

1. A circuit for generating electrical solitons, comprising:

a first amplifier having a gain variable according to at least a magnitude of a voltage at an output of the first amplifier, the first amplifier comprising at least one oscillator junction field effect transistor (JFET) that includes a gate of a semiconductor material doped to a first conductivity type formed on a channel of semiconductor material doped to a second conductivity type, the gate of the at least one oscillator JFET being coupled to an input of the first amplifier by a coupling capacitance;

a feedback non-linear transmission line (NLTL) coupled between the output and the input of the first amplifier; and

a pulse generator having a gain variable according to at least a magnitude of the voltage at the output of the first amplifier.

2. The circuit claim 1 , wherein:

the at least one oscillator JFET includes

a first oscillator JFET of a first channel conductivity type having a source coupled to a first power supply node, and a drain coupled to an intermediate node, and

a second oscillator JFET of a second channel conductivity type having a gate coupled to the intermediate node, a source coupled to a second power supply node, and a drain coupled to the output of the first amplifier.

3. The circuit of claim 1 , wherein:

the feedback NLTL comprises variable capacitors periodically coupled between two conductive lines, the variable capacitors providing a capacitance that varies according to the potential between the two conductive lines.

4. The circuit of claim 1 , wherein:

the pulse generator comprises at least one transmission JFET that includes a gate of a semiconductor material doped to the first conductivity type formed on a substrate of semiconductor material doped to the second conductivity type, the gate of the at least one transmission JFET being coupled to the input of the first amplifier; and

a transmission NLTL coupled to an output of the pulse generator, the transmission NLTL having a same repeating structure as the feedback NLTL.

5. The circuit of claim 4 , wherein:

the first amplifier includes a variable bias stage coupled between the drain and at least one gate of the at least one oscillator JFET, the variable bias stage generating a bias voltage that varies according to the potential at the intermediate node; and

the at least one transmission JFET has a gate coupled to the drain of the at least one oscillator JFET.

6. The circuit of claim 4 , further including:

the pulse generator is disabled and enabled according to an enable input; and

a main integrated circuit section including at least one data output coupled to the enable input of the pulse generator.

7. The circuit of claim 6 , wherein:

the main integrated circuit portion is selected from the group consisting of: a random access memory (RAM), a programmable read only memory (PROM), a logic circuit, and a programmable logic circuit.

8. The circuit of claim 4 , wherein:

the transmission NLTL is formed on a same substrate containing the first amplifier and pulse generator.

9. The circuit of claim 4 , wherein:

the transmission NLTL couples a first substrate containing the first amplifier and pulse generator to a second substrate different from the first substrate.

10. The circuit of claim 1 , further including:

the first amplifier and NLTL form portions of a first oscillator circuit that outputs a first signal having about a first frequency;

a second oscillator that outputs a second signal having about a second frequency, the second amplifier varying from the second frequency according to noise; and

a logic circuit for logically combining the first signal and the second signal to generate a pseudorandom sequence of pulses.