IP Library Granted Patent US 8,999,861
Granted Patent B1
US 8,999,861 · App. 13/469,249 · Granted Apr 7, 2015

Semiconductor structure with substitutional boron and method for fabrication thereof

Inventors: Lance Scudder (Sunnyvale, CA); Pushkar Ranade (Los Gatos, CA); Charles Stager (Austin, TX); Lucian Shifren (San Jose, CA); Dalong Zhao (San Jose, CA); U.C. Sridharan (San Jose, CA); Michael Duane (San Carlos, CA)
Assignee: SuVolta, Inc.
H01L21/02205
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Quick Facts
Patent No.
US 8,999,861
App. No.
13/469,249
Granted
Apr 7, 2015
Kind
B1
Abstract

A method for fabricating a semiconductor structure so as to have reduced junction leakage is disclosed. The method includes providing substitutional boron in a semiconductor substrate. The method includes preparing the substrate using a pre-amorphization implant and a carbon implant followed by a recrystallization step and a separate defect repair/activation step. Boron is introduced to the pre-amorphized region preferably by ion implantation.

Claims (14)

1. A method for fabricating a semiconductor structure on a semiconductor substrate, comprising:

masking portions of the substrate to form a pattern of transistors;

performing a pre-amorphization implant into selected open areas defining a channel stack underlying a gate for a plurality of transistor elements of a similar type;

performing a carbon ion implantation into the selected open areas in addition to the pre-amorphization implant;

performing a boron ion implantation into the selected open areas in addition to the carbon ion implantation so as to form a screening region for the transistor element;

performing a solid phase epitaxy after the carbon and boron ion implantations to cause the amorphized portions to transform into crystalline structures;

performing an activation anneal to activate the boron by rendering the boron substitutional;

forming a threshold voltage control layer on the boron screening region of the transistor element; and

forming an epitaxial channel layer on the threshold control layer of the transistor element.

2. The method of claim 1 , wherein the threshold voltage control layer is comprised of ion implanted boron.

3. The method of claim 1 , wherein the threshold voltage control layer is comprised of a fully substitutional in-situ doped epitaxial layer.

4. The method of claim 1 , wherein the activation anneal is a spike anneal performed at a temperature of 800° C. to 1500° C.

5. The method of claim 4 , wherein the spike anneal is performed after the solid phase epitaxy but prior to other thermal processes performed on the semiconductor substrate.

6. The method of claim 1 , wherein the pre-amorphization implant uses germanium.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: SU VOLTA, INC.
To: MIE FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 035508/0113 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2012
From: SCUDDER, LANCE; RANADE, PUSHKAR; STAGER, CHARLES; SHIFREN, LUCIAN; ZHAO, DALONG; SRIDHARAN, UC; DUANE, MICHAEL
To: SUVOLTA, INC.
Reel/Frame 028193/0346 →
Continuity (1)
Provisional Application 61518771 · May 11, 2011