Source/drain extension control for advanced transistors
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 19 atoms/cm 3 ′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
1. A semiconductor structure, comprising:
at least one transistor, the transistor having:
a gate with an effective gate length;
a source region;
a drain region;
an epitaxially grown channel layer below the gate and extending between the source region and the drain region;
a first highly doped layer below the channel layer and coextensive therewith, the first highly doped layer effective to set threshold voltage for the transistor;
a second highly doped layer below the first highly doped layer and coextensive therewith, the second highly doped layer effective to set a depletion depth for the transistor;
a third highly doped layer below the second highly doped layer and coextensive therewith, the third highly doped layer effective to function as a punch through suppression layer;
wherein the transistor is haloless.
2. The semiconductor structure of claim 1 , wherein the second highly doped layer has a dopant concentration of between about 5×10 18 to 1×10 20 atoms/cm 3 .
3. The semiconductor structure of claim 1 , wherein the first highly doped layer has a dopant concentration of between about 1×10 18 to 1×10 19 atoms/cm 3 .
4. The semiconductor structure of claim 1 , wherein the second highly doped layer is electrically coupled to a circuit designed to produce a body bias to the transistor.
5. The semiconductor structure of claim 4 , wherein the body bias may be static or dynamic.
6. The semiconductor structure of claim 1 , further comprising
a shallow trench isolation region to separate and isolate the transistor from another transistor in the semiconductor structure.
7. The semiconductor structure of claim 1 , wherein the second highly doped layer has a dopant concentration greater than each of the dopant concentrations of the first highly doped layer and the third highly doped layer.
8. The semiconductor structure of claim 1 , wherein the channel layer is undoped.
9. The semiconductor structure of claim 1 , wherein the transistor includes a gate spacer disposed directly on the gate.
10. The semiconductor structure of claim 1 , wherein the threshold voltage of the transistor is established by a thickness, dopant concentration, and distance from the gate of the first highly doped layer.
11. A semiconductor structure, comprising:
at least one transistor, the transistor having:
a gate with an effective gate length Lg, the gate including gate spacers;
a source region and a drain region, the source region and the drain region being formed by using the gate spacers as a positioning mask;
an epitaxially grown channel layer below the gate and extending between the source region and the drain region, the epitaxially grown channel including applied stress;
a first highly doped layer below the channel layer and coextensive therewith, the first highly doped layer effective to set a depletion depth for the transistor, the first highly doped layer being separated from the gate by a defined vertical distance of Lg/1.5 to Lg/5;
a second highly doped layer below the first highly doped layer and coextensive therewith, the second highly doped layer effective to function as a punch through suppression layer; and
a third highly doped layer above the second highly doped layer and coextensive therewith;
wherein the first highly doped layer has the highest dopant concentration among the first, second, and third highly doped layers.
12. The semiconductor structure of claim 11 , wherein the first highly doped layer has a dopant concentration of between about 5×10 18 to 1×10 20 atoms/cm 3 .
13. The semiconductor structure of claim 11 , wherein the first highly doped layer is electrically coupled to a circuit designed to produce a body bias to the transistor.
14. The semiconductor structure of claim 13 , wherein the body bias may be static or dynamic.
15. The semiconductor structure of claim 11 , further comprising:
a shallow trench isolation region to separate and isolate the transistor from another transistor in the semiconductor substrate.
16. The semiconductor structure of claim 11 , wherein the third highly doped layer is above the first highly doped layer.
17. The semiconductor structure of claim 16 , wherein the third highly doped layer has a dopant concentration of between about 1×10 18 to 1×10 19 atoms/cm 3 .
18. The semiconductor structure of claim 11 , wherein the third highly doped layer has a dopant concentration greater than a dopant concentrations of the second highly doped layer.
19. The semiconductor structure of claim 11 , wherein the channel layer is undoped.
20. The semiconductor structure of claim 11 , wherein the gate spacers are disposed directly on the gate.