Source/drain extension control for advanced transistors
A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×10 19 atoms/cm 3 , or alternatively, less than one-quarter the dopant concentration of the source and the drain.
1. A semiconductor die, comprising:
a plurality of transistors, the plurality of transistors each having:
a gate with an effective gate length;
a source region;
a drain region;
an epitaxially grown channel layer below the gate and extending between the source region and the drain region;
a first highly doped layer below the channel layer and coextensive therewith, the first highly doped layer effective to set a depletion depth for said plurality of transistors; and
wherein some of the plurality of transistors have a second highly doped layer below the channel layer and above the first highly doped layer;
wherein some of the plurality of transistors include a source and drain extension region; and
wherein some of the plurality of transistors are haloless.
2. A semiconductor die as in claim 1 , wherein the first highly doped layer has a dopant concentration of between 5×10 18 to 1×10 20 atoms/cm 3 .
3. A semiconductor die as in claim 1 , wherein the second highly doped layer has a dopant concentration of between 1×10 18 to 1×10 19 atoms/cm 3 .
4. A semiconductor die as in claim 1 , wherein some of the plurality of transistors have another highly doped layer below the first highly doped layer and coextensive therewith, the another highly doped layer effective to function as a punch through suppression layer.
5. A semiconductor die as in claim 1 , wherein the epitaxially grown channel layer is undoped.
6. A semiconductor die as in claim 1 , wherein the source and drain extensions are formed by ion implantation.
7. A semiconductor die as in claim 1 , wherein the source region and the drain region are formed by ion implantation.
8. A semiconductor die as in claim 1 , wherein the source region and the drain region are formed by selective epitaxial growth.
9. A semiconductor die as in claim 1 , wherein the source region and the drain region are raised.
10. A semiconductor die as in claim 1 , wherein the second highly doped layer is formed on a substrate.
11. A semiconductor structure on a bulk silicon substrate, the structure comprising:
a transistor having a gate, a source region and a drain region;
an undoped epitaxially grown channel layer below the gate and extending between the source region and the drain region;
a first highly doped layer below the channel layer, the highly doped layer extending laterally across the channel layer;
a second highly doped layer below the first highly doped layer and coextensive therewith, the second highly doped layer being doped to a concentration sufficient to set the depletion width for the transistor;
a third highly doped layer below the second highly doped layer and coextensive therewith, the third highly doped layer being doped to a concentration sufficient to serve as a punch through suppression layer; and
wherein the transistor is haloless.
12. A semiconductor structure as in claim 11 , wherein the punch through suppression layer has a dopant concentration less than the second highly doped layer.
13. A semiconductor structure as in claim 11 , wherein the first highly doped layer is coextensive with the channel layer.
14. A semiconductor structure as in claim 11 , wherein the first highly doped layer and the second highly doped layers are separate distinct layers.
15. A semiconductor structure as in claim 11 , wherein the source region and the drain region further include respective source and drain extensions.
16. A semiconductor structure as in claim 15 , wherein the source and drain extensions are formed by ion implantation.
17. A semiconductor structure as in claim 11 , wherein the source region and the drain region are formed by ion implantation.
18. A semiconductor structure as in claim 11 , wherein the source region and the drain region are formed by selective epitaxial growth.
19. A semiconductor die as in claim 1 , wherein the second highly doped layer has a dopant concentration of between 5×10 18 to 1×10 20 atoms/cm 3 .
20. A semiconductor die as in claim 1 , wherein the first highly doped layer has a dopant concentration of between 1×10 18 to 1×10 19 atoms/cm 3 .