Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being different from power supply voltages of the DRAM; and peripheral circuits formed in the same substrate as the at least one DRAM array, the peripheral circuits comprising deeply depleted channel (DDC) transistors having bodies coupled to receive the body bias voltage, each DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region.
1. A dynamic random access memory (DRAM), comprising:
at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor;
a body bias control circuit configured to generate a body bias voltage from a bias supply voltage, the body bias voltage being different from a power supply voltage of the DRAM; and
peripheral circuits formed in the same substrate as the at least one DRAM cell array, the peripheral circuits having at least one deeply depleted channel (DDC) transistor having a body coupled to receive the body bias voltage, the DDC transistor having a screening region of a first conductivity type formed below a substantially undoped channel region, the screening region having a first dopant concentration that is no less than 1×10 18 dopant atoms/cm 3 and that is different from a second dopant concentration of a substrate portion or well containing the DDC transistor; wherein:
the peripheral circuits comprise a digital delay line circuit including at least a fine delay circuit having a plurality of delay stages arranged in series, each delay stage including DDC transistors; and
the body bias control circuit is a delay control circuit configured to apply different body biases to the DDC transistors of the delay stages in response to a delay set value.
2. The DRAM of claim 1 , wherein:
the body bias control circuit comprises a digital-to-analog converter (DAC) and the delay set value comprises a digital value input to the (DAC).
3. The DRAM of claim 1 , wherein:
the digital delay line circuit further includes
a coarse delay circuit configured to introduce any of a plurality of coarse delays into an input signal, and
the fine delay circuit introduces any of a plurality of fine delays into the input signal; wherein
the coarse delays have a same first duration, the fine delays have a same second duration, and the coarse delays consist of N fine delays, where N is an integer greater than one.