System and method for routing connections with improved interconnect thickness

1. A method for modeling a circuit, comprising:

receiving, at a computing machine, a netlist that defines a plurality of connections between a plurality of circuit elements, wherein the netlist is associated with one or more design rules;

generating, by the computing machine, a circuit model based on the netlist, wherein the circuit model comprises a model of one or more of the circuit elements;

determining, by the computing machine, a wire width associated with at least a selected connection based, at least in part, on the design rules associated with the netlist;

determining, by the computing machine, a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness;

routing, by the computing machine, the selected connection in the circuit model based on the wire width associated with the connection and the wire thickness associated with the connection; and

storing, by the computing machine, the circuit model in an electronic storage media;

wherein at least one of the circuit elements comprises a junction field effect transistor (JFET) logic device that includes a JFET operable to turn on when a voltage differential of 0.5 volts is applied across a gate terminal and a source terminal of the JFET.

2. The method of claim 1 , wherein the wire thickness associated with the selected connection is approximately equal to the wire width associated with the connection.

3. The method of claim 1 , wherein the wire thickness associated with the selected connection is within a range from approximately 60 nanometers to approximately 70 nanometers.

4. The method of claim 1 , wherein determining a wire thickness associated with a minimal delay comprises determining a wire thickness within a range of approximately 60 nanometers to 70 nanometers.

5. The method of claim 1 , further comprising:

calculating a wire length associated with at least a selected one of the plurality of connections; and

wherein determining a wire thickness comprises determining a wire thickness associated with a minimal signal delay for the calculated wire length.

6. The method of claim 5 , wherein:

calculating the wire length comprises calculating an average wire length associated with two or more of the connections;

determining the wire width comprises determining a wire width associated with the connections based, at least in part, on the design rules associated with the netlist;

determining the wire thickness comprises determining the wire thickness associated with a minimum signal delay for the calculated average wire length; and

routing the selected connection comprises routing the connections in the circuit model based on the wire width associated with the connections and the wire thickness associated with the minimum signal delay for the calculated average wire length.

7. The method of claim 1 , wherein the circuit elements comprise at least one circuit element of a first device type and at least one circuit element of a second device type, and wherein determining a wire thickness associated with the selected connection comprises:

identifying a device type of an output device associated with the selected connection; and

determining a wire thickness based on the device type of the output device.

8. The method of claim 7 , wherein the circuit element of the first device type comprises a junction field effect transistor (JFET) logic device and the circuit element of the second device type comprises a metal-oxide semiconductor field effect transistor (MOSFET) logic device.

9. The method of claim 8 , wherein determining a wire thickness based on the device type of the output device comprises:

determining a wire thickness equal to a first wire thickness if the output device comprises a JFET logic device; and

determining a wire thickness equal to a second wire thickness if the output device comprises a MOSFET logic device, wherein the second wire thickness is greater than the first wire thickness.

10. A non-transitory computer-readable storage medium including code for modeling a circuit, the code operable when execute to:

receive a netlist that defines a plurality of connections between a plurality of circuit elements, wherein the netlist is associated with one or more design rules;

generate a circuit model based on the netlist, wherein the circuit model comprises a model of one or more of the circuit elements;

determine a wire width associated with at least a selected connection based, at least in part, on the design rules associated with the netlist;

determine a wire thickness associated with the selected connection based, at least in part, on a signal delay associated with the wire thickness;

route the selected connection in the circuit model based on the wire width associated with the connection and the wire thickness associated with the connection; and

store the circuit model in an electronic storage media;

wherein at least one of the circuit elements comprises a junction field effect transistor (JFET) logic device that includes a JFET operable to turn on when a voltage differential of 0.5 volts is applied across a gate terminal and a source terminal of the JFET.

11. The computer software product of claim 10 , wherein the wire thickness associated with the selected connection is approximately equal to the wire width associated with the connection.

12. The computer software product of claim 10 , wherein the wire thickness associated with the selected connection is approximately equal to a minimum wire thickness associated with the circuit.

13. The computer software product of claim 10 , wherein the computer instructions are operable to determine a wire thickness associated with a minimal delay by determining a wire thickness within a range of approximately 60 nanometers to 70 nanometers.

14. The computer software product of claim 10 , wherein the computer instructions are further operable to calculate a wire length associated with at least a selected one of the plurality of connections; and wherein the computer instructions are operable to determine a wire thickness by determining a wire thickness associated with a minimal signal delay for the calculated wire length.

15. The computer software product of claim 14 , wherein the computer instructions are operable to:

calculate a wire length by calculating an average wire length associated with two or more of the connections;

determine the wire width by determining a wire width associated with the connections based, at least in part, on the design rules associated with the netlist;

determine the wire thickness by determining the wire thickness associated with a minimum signal delay for the calculated average wire length; and

route the selected connection by routing the connections in the circuit model based on the wire width associated with the connections and the wire thickness associated with the minimum signal delay for the calculated average wire length.

16. The computer software product of claim 10 , wherein the circuit elements comprise at least one circuit element of a first device type and at least one circuit element of a second device type, and wherein the processor instructions are operable to determine a wire thickness associated with the selected connection by:

identifying a device type of an output device associated with the selected connection; and

determining a wire thickness based on the device type of the output device.

17. The computer software product of claim 16 , wherein the circuit element of the first device type comprises a junction field effect transistor (JFET) logic device and the circuit element of the second device type comprises a metal-oxide semiconductor field effect transistor (MOSFET) logic device.

18. The computer software product of claim 17 , wherein the processor instructions are further operable to determine a wire thickness based on the device type of the output device by:

determining a wire thickness equal to a first wire thickness if the output device comprises a JFET logic device; and

determining a wire thickness equal to a second wire thickness if the output device comprises a MOSFET logic device, wherein the second wire thickness is greater than the first wire thickness.