Method for providing temperature uniformity of rapid thermal annealing

1. A method for annealing a semiconductor device having a polysilicon gate contact region formed on a substrate, a polysilicon source contact region formed on the substrate, and a polysilicon drain contact region formed on the substrate, the method comprising:

forming dielectric material on the substrate in gaps between the polysilicon gate contact region, the polysilicon source contact region, and the polysilicon drain contact region;

polishing the dielectric material;

depositing a layer of semi-transparent material on the dielectric material, the polysilicon gate contact region, the polysilicon source contact region, and the polysilicon drain contact region; and

annealing the semiconductor device.

2. The method of claim 1 , wherein the dielectric material comprises silicon dioxide.

3. The method of claim 1 , wherein the semi-transparent material comprises silicon nitride.

4. The method of claim 1 , wherein the semi-transparent material comprises silicon dioxide.

5. The method of claim 1 , wherein the semi-transparent material comprises at least one of: Al 2 O 3 , AlON, CaF 2 , HfO 2 , and Y 2 O 2 .

6. The method of claim 1 , wherein:

annealing is performed using a flash lamp operating in the 200 nm to 1100 nm wavelength spectrum; and

the semi-transparent material has a low dielectric constant for at least a portion of the 200 nm to 1100 nm wavelength spectrum.

7. The method of claim 1 , wherein at least one of the polysilicon regions is approximately 50 nm tall.

8. The method of claim 1 , wherein the thickness of the semi-transparent material is selected based on a desired temperature rise to be achieved in at least one of the polysilicon regions and in the substrate beneath the dielectric material.

9. The method of claim 1 , wherein increasing the thickness of the layer of semi-transparent material causes an increase in temperature in at least one of the polysilicon regions and a decrease in temperature in the substrate beneath the dielectric material.

10. The method of claim 1 , wherein decreasing the thickness of the layer of semi-transparent material causes a decrease in temperature in at least one of the polysilicon regions and an increase in temperature in the substrate beneath the dielectric material.

11. The method of claim 1 , wherein depositing a layer of the semi-transparent material comprises:

depositing a first thickness of the semi-transparent material on the surface of at least one of the polysilicon regions; and

depositing a second thickness of the semi-transparent material on the surface of the dielectric material.

12. The method of claim 1 , wherein the semiconductor device comprises a junction field effect transistor or a CMOS transistor.

13. The method of claim 1 , wherein the semiconductor device includes spacers on sidewalls of the polysilicon gate contact region and the layer of semi-transparent material comprises a first layer of semi-transparent material, the method further comprising depositing a second layer of semi-transparent material on the first layer of semi-transparent material.

14. The method of claim 3 , wherein the first layer of semi-transparent material comprises silicon dioxide and the second layer of semi-transparent material comprises silicon nitride.

15. The method of claim 3 , wherein the first layer of semi-transparent material comprises silicon nitride and the second layer of semi-transparent material comprises silicon dioxide.

16. The method of claim 1 , wherein annealing the semiconductor device comprises rapid flash annealing the semiconductor device.