IP Library Granted Patent US 7,843,018
Granted Patent B2
US 7,843,018 · App. 12/363,796 · Granted Nov 30, 2010

Transistor providing different threshold voltages and method of fabrication thereof

Assignee: SuVolta, Inc.
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Quick Facts
Patent No.
US 7,843,018
App. No.
12/363,796
Granted
Nov 30, 2010
Kind
B2
Abstract

A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of the second portion allows for an increased ON current. Despite the increase attained in the ON current, the higher threshold voltage of the first portion maintains or lowers a relatively low OFF current for the transistor.

Claims (35)

1. A transistor, comprising:

a source region formed in a semiconductor substrate;

a drain region formed in the semiconductor substrate and spaced apart from the source region; and

a channel region formed in the semiconductor substrate between the source region and the drain region, the channel region having a first portion with a first depth and a second portion with a second depth different than the first depth, wherein the first portion has an amount of dopant at the first depth and the second portion has approximately the same amount of the dopant at the second depth such that the second portion has a different threshold voltage than the first portion.

2. The transistor of claim 1 , wherein the second portion provides a higher threshold voltage than the first portion.

3. The transistor of claim 1 , wherein the first portion has a first length and the second portion has a second length, the second length being smaller than the first length.

4. The transistor of claim 3 , wherein the second length is determined by an equation α×L and the first length is determined by an equation L−(α×L), where L is a length of the channel region and a is a fraction less than one.

5. The transistor of claim 1 , wherein the second portion is in closer proximity to the source region of the transistor than the first portion.

6. The transistor of claim 1 , wherein the second portion has a lesser depth than the first portion.

7. The transistor of claim 1 , wherein the channel region has a third portion, the third portion providing a different threshold voltage than the first portion.

8. The transistor of claim 7 , wherein the first portion separates the second portion from the third portion.

9. A transistor, comprising:

a source region formed in a semiconductor substrate;

a drain region formed in the semiconductor substrate and spaced apart from the source region; and

a channel region formed in the semiconductor substrate between the source region and the drain region, the channel region having a first portion with a first depth and a second portion with a second depth different than the first depth, wherein:

the first portion has an amount of dopant at the first depth and the second portion has approximately the same amount of the dopant at the second depth;

the second portion has a higher threshold voltage than the first portion; and

the second portion has a smaller length than the first portion.

10. The transistor of claim 9 , wherein the length of the second portion is determined by an equation α×L and the length of the first portion is determined by an equation L−(α×L), where L is a length of the channel region and a is a fraction less than one.

11. The transistor of claim 9 , wherein the second portion is in closer proximity to the source region of the transistor than the first portion.

12. The transistor of claim 9 , wherein the second portion has a lesser depth than the first portion.

13. The transistor of claim 9 , wherein the channel region has a third portion, the third portion providing a higher threshold voltage than the first portion.

14. The transistor of claim 13 , wherein the first portion separates the second portion from the third portion.

15. A transistor, comprising:

a source region formed in a semiconductor substrate;

a drain region formed in the semiconductor substrate and spaced apart from the source region; and

a channel region formed in the semiconductor substrate between the source region and the drain region, the channel region having a first portion with a first depth, a second portion with a second depth different than the first depth, and a third portion, wherein the first portion has an amount of dopant at the first depth and the second portion has approximately the same amount of the dopant at the second depth, and the first portion has a different threshold voltage than the second portion and the third portion.

16. The transistor of claim 15 , wherein the first portion separates the second portion from the third portion.

17. The transistor of claim 15 , wherein the first portion provides a lower threshold voltage than the second portion and the third portion.

18. The transistor of claim 15 , wherein:

the first portion has a first length;

the second portion has a second length;

the third portion has a third length; and

the second length and the third length are smaller than the first length.

19. The transistor of claim 15 , wherein the second portion has a lesser depth than the first portion.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: SU VOLTA, INC.
To: MIE FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 035508/0113 →
CHANGE OF NAME Recorded Sep 10, 2010
From: DSM SOLUTIONS, INC.
To: SUVOLTA, INC.
Reel/Frame 024970/0347 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2009
From: MIN, SUNG-KI
To: DSM SOLUTIONS, INC.
Reel/Frame 022186/0165 →
Continuity (2)
Division 1174397300 · May 3, 2007
Related Publication 20090134475A1 · May 28, 2009