Method of producing and operating a low power junction field effect transistor
A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth. The CJFET operates at a power supply with a lesser value than the voltage drop across a forward-biased diode having a reduced switching power as compared to said CMOS inverter and having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
1. A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth, the method comprising the steps of:
having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a CMOS inverter of similar linewidth;
operating at a power supply with a lesser value than the voltage drop across a forward-biased diode;
having a reduced switching power as compared to said CMOS inverter; and
having a propagation delay for said CJFET inverter that is at least comparable to the corresponding delay of said CMOS inverter.
2. The method in claim 1 , wherein, as compared to said CMOS inverter, said CJFET inverter is less subject to various electrical degradation mechanism.
3. The method in claim 2 , wherein said various electrical degradation mechanism comprising a gate oxide degradation.
4. The method of claim 2 , wherein said various electrical degradation mechanism comprising an electrostatic discharge phenomena.
5. The method in claim 1 , wherein said small linewidth is less than 100 nm.
6. The method in claim 1 , wherein said small linewidth is less than 45 nm.
7. The method in claim 6 , wherein said CJFET inverter has a lesser gate current as compared to the corresponding gate current of said CMOS inverter built with conventional gate dielectric.
8. The method in claim 7 , wherein said lesser CJFET gate current is more than ten times lower than the corresponding CMOS current.
9. The method in claim 1 , wherein said power supply is about 0.5 Volt or below.
10. The method in claim 1 , wherein said propagation delay is at least three times less than a corresponding delay of said CMOS inverter.
11. The method in claim 1 , wherein said CJFET inverter further comprising a first junction field transistor (JFET 1 ) adjacent, within the same semiconductor substrate, to a second junction field transistor (JFET 2 ), wherein:
said JFET 1 has a n-type channel region and said JFET 2 has a p-type channel region.
12. The method in claim 11 , wherein said JFET 1 is formed within a p-type well region and said JFET 2 formed within in a n-type well region.
13. The method in claim 12 , wherein said p-type and n-type well regions are embedded in said same semiconductor substrate.
14. The method in claim 13 , wherein said n-type well region is further embedded into said p-type well region.
15. The method in claim 14 , wherein said JFET 1 and said JFET 2 each further comprising a gate region located between the appropriate source and drain regions of the corresponding JFET transistors; and all well, gate, source and drain regions are being embedded into said same semiconductor substrate.
16. The method of claim 1 , further comprising:
biasing a well voltage of the CJFET to reduce power supply leakage current.