Transistor with threshold voltage set notch and method of fabrication thereof
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σV T compared to conventional bulk CMOS and can allow the threshold voltage V T of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the V T setting within a precise range. This V T set range may be extended by appropriate selection of metals so that a very wide range of V T settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control V T (with a low σV T ) and V DD , so that the body bias can be tuned separately from V T for a given device.
1. A method for forming an integrated circuit die containing multiple device types, comprising:
forming a plurality of doped wells, at least some of the doped wells being secondarily doped to form screening layers for a first device type, at least some of the doped wells supporting a second device type;
forming a threshold voltage tuning layer on the screening layers of the first device type doped to provide a threshold voltage set notch;
forming a first channel layer on the threshold voltage tuning layer of the first device type;
forming a second channel layer on doped wells of the second device type; and
forming a plurality of gate stacks on the first and second channel layers, at least some gate stacks having a first work function and other gate stacks having a second work function;
wherein forming the threshold tuning layer comprises implanting dopants such that a vertical dopant profile created by the first channel layer, the threshold voltage tuning layer, and the screening layer the threshold voltage set notch with a shallow notch configuration.
2. The method of claim 1 , wherein forming the threshold voltage tuning layer comprises implanting dopants such that a vertical dopant profile created by the channel layer, the threshold voltage tuning layer, and the screening layer provides the threshold voltage set notch with a reverse notch configuration in addition to the shallow notch configuration.
3. The method of claim 1 , wherein forming the threshold voltage tuning layer comprises implanting dopants such that a vertical dopant profile created by the channel layer, the threshold voltage tuning layer, and the screening layer provides the threshold voltage set notch with multiple notches including the shallow notch.
4. The method of claim 1 , wherein forming the threshold voltage tuning layer comprises implanting dopants such that a vertical dopant profile created by the channel layer, the threshold voltage tuning layer, and the screening layer provides the threshold voltage set notch with multiple reverse notches in addition to the shallow notch configuration.
5. The method of claim 1 , wherein forming the first channel layer, the threshold voltage tuning layer, and the screening layer comprises implanting dopants to form a deeply depleted channel (DDC) device.
6. The method of claim 1 , wherein the first and second channel layers are substantially undoped.
7. The method of claim 1 , wherein the gate stacks having the first work function and the gate stacks having the second work function both comprise metal.
8. The method of claim 1 , further comprising:
forming a shallow well in at least one of the plurality of doped wells.
9. The method of claim 1 , further comprising:
forming a body tap coupled to at least one of the doped wells, wherein the body tap is operable to selectively apply a bias thereto to adjust the threshold voltage.