IP Library Granted Patent US 7,648,898
Granted Patent B2
US 7,648,898 · App. 12/033,487 · Granted Jan 19, 2010

Method to fabricate gate electrodes

Assignee: DSM Solutions, Inc.
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Quick Facts
Patent No.
US 7,648,898
App. No.
12/033,487
Granted
Jan 19, 2010
Kind
B2
Abstract

A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of the layer of nitride to the first layer of oxide. The method further comprises depositing a second layer of oxide and planarizing the oxide to expose at least a portion of the layer of nitride. The method further comprises stripping at least a portion of the layer of nitride to create one or more notches and removing at least a portion of the first layer of oxide. The method further comprises depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into at least one of the one or more notches.

Claims (35)

1. A method for fabricating a semiconductor device, comprising:

forming a channel of a transistor, wherein the channel has a first conductivity type;

depositing a first layer of oxide on a least a portion of the channel;

depositing a layer of nitride on the first layer of oxide;

etching the nitride, wherein at least a portion of the layer of nitride is etched to the first layer of oxide;

depositing a second layer of oxide on the layer of nitride and the first layer of oxide;

planarizing the second layer of oxide to expose at least a portion of the layer of nitride;

stripping at least a portion of the layer of nitride to create one or more notches and to expose at least a portion of the first layer of oxide;

removing at least a portion of the first layer of oxide; and

depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into one or more notches created by stripping at least a portion of the layer of nitride.

2. The method of claim 1 , wherein the method further comprises planarizing the polysilicon and at least a portion of the second layer of oxide.

3. The method of claim 1 , wherein forming a channel of a transistor comprises forming a channel in a shallow trench isolation structure.

4. The method of claim 1 , wherein the first layer of oxide comprises a thickness at least 10 Å.

5. The method of claim 1 , wherein the layer of nitride is at least 300 Å.

6. The method of claim 5 , wherein the second layer of oxide is at least 900 Å.

7. The method of claim 1 , further comprising implanting a second conductivity doping type in the polysilicon residing within at least one of the one or more notches.

8. The method of claim 1 , further comprising doping the polysilicon with material of a first conductivity type.

9. The method of claim 1 , wherein planarizing the oxide comprises using a chemical-mechanical planarization process.

10. The method of claim 1 , wherein etching the nitride comprises using a photoresist.

11. The method of claim 1 , wherein the depth of the channel of the transistor is less than 400 Å.

12. The method of claim 1 , wherein etching the nitride comprises stopping the nitride etch before etching into the channel of a transistor to prevent channel cut-off.

13. The method of claim 1 , wherein planarizing the oxide to expose at least a portion of the layer of nitride comprises using nitride as an etch stop layer.

14. The method of claim 1 , wherein planarizing the polysilicon and at least a portion of the second layer of oxide comprises using oxide as an etch stop layer.

15. A method for fabricating a semiconductor device, comprising:

forming a channel of a transistor, wherein the channel has a first conductivity type;

depositing a first layer of oxide on at least a portion of the channel;

depositing a layer of nitride on the layer of oxide;

etching the nitride, wherein at least a portion of the layer of nitride is etched to the first layer of oxide and the first layer of oxide stops the nitride etch before etching into the channel;

depositing a second layer of oxide on the layer of nitride and the first layer of oxide;

planarizing the second layer of oxide to expose at least a portion of the layer of nitride;

stripping at least a portion of the layer of nitride to create one or more notches and to expose at least a portion of the first layer of oxide;

removing at least a portion of the first layer of oxide;

depositing a layer of polysilicon, wherein at least a portion of the layer of polysilicon is deposited into one or more notches created by stripping at least a portion of the layer of nitride; and

planarizing the polysilicon and at least a portion of the second layer of oxide.

16. The method of claim 15 , wherein the depth of the channel of the transistor is less than 400 Å.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: SU VOLTA, INC.
To: MIE FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 035508/0113 →
CHANGE OF NAME Recorded Jan 6, 2010
From: DSM SOLUTIONS, INC.
To: SUVOLTA, INC.
Reel/Frame 023731/0988 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNOR PREVIOUSLY RECORDED ON REEL 020528 FRAME 0038. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 2, 2009
From: BANNA, SRINIVASA R.
To: DSM SOLUTIONS, INC.
Reel/Frame 022189/0518 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2008
From: BANNA, SRINIVASA B.
To: DSM SOLUTIONS, INC.
Reel/Frame 020528/0038 →
Continuity (1)
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