Analog circuits having improved insulated gate transistors, and methods therefor
A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.
1. A circuit, comprising:
at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and
a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein
each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type, the highly doped screening region formed below the channel region and extending laterally between the source and drain.
2. The circuit of claim 1 , wherein:
the circuit comprises a current mirror circuit that provides an output current in response to a reference current;
the pair of DDC transistors have gates commonly coupled to one another and to a drain of a first of the DDC transistors, and bodies commonly coupled to their gates; and
the bias circuit is configured to provide the reference current to the drain of the first DDC transistor.
3. The circuit of claim 1 , further including:
the circuit comprises an operational amplifier circuit configured to amplify an input voltage received at input nodes;
the pair of DDC transistors includes
a first input DDC transistor with a gate coupled to a first input node, and
a second input DDC transistor with a gate coupled to a second input node; and
an output stage comprising a driver transistor coupled to an output node, the driver transistor being controlled in response to a current flowing through the first input DDC transistor.
4. The circuit of claim 3 , wherein:
the bodies of the first and second input DDC transistors have bodies commonly coupled to a source of one of the input DDC transistors.
5. The circuit of claim 3 , wherein:
the body of the first input DDC transistor is coupled to its gate; and
the body of the second input DDC transistor is coupled to its gate.
6. The circuit of claim 3 , wherein:
the bias circuit comprises a current mirror circuit formed of at least one pair of mirror DDC transistors of a conductivity type opposite to that of the input DDC transistors, the mirror DDC transistors having gates commonly coupled to one another and to a drain of a first of the mirror DDC transistors, and bodies commonly coupled to their gates.
7. The circuit of claim 1 , wherein:
the circuit is configured to operate with a power supply voltage of less-than-or-equal to 0.5 volts.
8. The circuit of claim 1 , wherein:
the highly doped screening region has a dopant concentration of no less than 5×10 18 .
9. The circuit of claim 1 , wherein:
the highly doped screening region contacts the source and drain.
10. A circuit, comprising:
a plurality of inverting stages coupled to one another in series, an output of a last stage being coupled to an input of a first stage; and
each stage comprising at least two deeply depleted channel (DDC) transistors having gates coupled to a stage input, and configured to drive a stage output between two different voltages; wherein
each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type, the highly doped screening region formed below the channel region and extending laterally between the source and drain.
11. The circuit of claim 10 , wherein:
each stage comprises a first DDC transistor of a first conductivity type and a second DDC transistor of a second conductivity type having drains commonly coupled to the stage output.
12. The circuit of claim 10 , wherein:
each stage includes the bodies of the DDC transistors coupled to their gates.
13. The circuit of claim 10 , further including:
a stage capacitance coupled between each stage, each stage capacitance comprising a load DDC transistor.
14. The circuit of claim 13 , wherein:
each load DDC transistor has gate coupled to a first capacitance terminal and a source and drain commonly coupled to a second capacitance terminal.
15. The circuit of claim 13 , wherein:
each stage capacitance comprises a varactor, with the body of each load DDC transistor coupled to a first voltage source and the source and drain of each load transistor coupled to a second voltage source; wherein
the capacitance of the varactor varies in response to the first and second voltage sources.
16. The circuit of claim 10 , further including:
the circuit is configured to operate with a power supply voltage of less-than-or-equal to 0.5 volts.
17. The circuit of claim 10 , wherein:
the highly doped screening region contacts the source and drain.
18. A circuit, comprising:
at least one varactor element comprising at least a first deeply depleted channel (DDC) transistor having a gate coupled to a first terminal, source and drain coupled to a second terminal, and a body coupled to a third terminal;
a first bias circuit coupled to apply a first bias voltage to the third terminal; and
a second bias circuit coupled to apply a second bias voltage to the second terminal; wherein
each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type formed below the channel region and extending laterally between the source and drain, and wherein a capacitance between the first and second terminals varies in response to the first and second bias voltages.
19. The circuit of claim 18 , wherein:
each varactor element further includes a second DDC transistor having a gate coupled to a fourth terminal, source and drain coupled to the second terminal, and a body coupled to the third terminal; wherein
a capacitance between the first and fourth terminals varies in response to the first and second bias voltages.
20. The circuit of claim 18 , further including:
a plurality of inverting stages coupled to one another in series, an output of a last stage being coupled to an input of a first stage; and
the at least one varactor element includes a plurality of varactor elements, each having a first terminal coupled to an output of each stage.
21. The circuit of claim 18 , further including:
the varactor element further includes a second DDC transistor having a gate coupled to a fourth terminal, source and drain coupled to the second terminal, and a body coupled to the third terminal;
a first inductor coupled between the first terminal and a power supply terminal; and
a second inductor coupled between the fourth terminal and the power supply terminal.
22. The circuit of claim 18 , wherein:
the at least one varactor element has a capacitance tuning range more than 15% greater than the tuning range of a varactor element formed with a same sized transistor that does not include a substantially undoped channel region or a highly doped screening region.
23. The circuit of claim 18 , wherein:
the highly doped screening region contacts the source and drain.