Semiconductor device storage cell structure, method of operation, and method of manufacture
The invention can include at least one storage cell having a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type. A storage cell can also include at least a first source/drain region and a second source/drain region separated from one another by the channel region. A control gate structure, comprising a semiconductor layer doped to the first conductivity type can be formed over a substrate surface. The control gate structure can be in contact with the channel region. Such a storage cell can be more compact and/or provide longer data retention times than conventional storage cells, such as many conventional dynamic random access memory (DRAM) type cells.
1. A semiconductor device, comprising:
at least one storage cell, comprising:
a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type;
at least a first source/drain region and a second source/drain region separated from one another by the channel region; and
a control gate structure, comprising a semiconductor layer doped to the first conductivity type and formed over a substrate surface, the control gate structure being in contact with the channel region, and further including:
a discharge channel comprising a semiconductor region doped to the first conductivity type that contacts the store gate and a bulk region comprising a semiconductor material doped to the first conductivity type, the discharge channel having a dopant concentration less than that of the store gate and the bulk region.
2. The semiconductor device of claim 1 , wherein:
the substrate comprises a semiconductor material; and
the store gate structure is formed within the substrate.
3. The semiconductor device of claim 2 , further including:
an isolation structure formed in the substrate; and
a portion of the store gate is in contact with the isolation structure.
4. The semiconductor device of claim 2 , wherein:
the store gate is formed below the substrate surface.
5. The semiconductor device of claim 4 , wherein:
the store gate is surrounded by semiconductor material doped to the second conductivity type.
6. The semiconductor device of claim 1 , wherein:
the at least first source/drain region comprises a semiconductor layer doped to the second conductivity type and formed over and in contact with the substrate surface.
7. The semiconductor device of claim 6 , wherein:
the at least first source/drain region and control gate structure comprise structures patterned from a same semiconductor layer.
8. The semiconductor device of claim 1 , wherein:
the at least first source/drain region comprises a portion of the substrate doped to the first conductivity type and having a higher dopant concentration than the channel region.
9. The semiconductor device of claim 1 , wherein:
the control gate structure is formed over the store gate structure in a direction perpendicular to the substrate surface.
10. The semiconductor device of claim 1 , wherein:
the at least one storage cell includes a plurality of storage cells arranged into at least one row, the storage cells of the same row having control gates structures commonly connected to a conductive word line.
11. The semiconductor device of claim 10 , wherein:
the control gates and word line of the same row comprise a contiguous structure patterned from a same semiconductor layer.
12. The semiconductor device of claim 10 , further including:
the plurality of storage cells are arranged into multiple rows, each row having a corresponding word line; and
a row decoder that selectively provides gate voltages to the word lines in response to at least a portion of a received address value.
13. The semiconductor device of claim 10 , wherein:
the plurality of storage cells are further arranged into at least one column, the storage cells of the same column having at least first source/drain regions commonly connected to a bit line.
14. The semiconductor device of claim 13 , wherein:
the plurality of storage cells are arranged into multiple columns, each column having a corresponding bit line; and
a column decoder that selectively couples the bit lines to a common node in response to at least a portion of a received address value.
15. The semiconductor device of claim 13 , wherein:
the storage cells of the same column having at least second source/drain regions commonly connected to a source line.
16. The semiconductor device of claim 13 , further including:
a current sense amplifier coupled to the bit line that generates a data value based on the magnitude of a current drawn by the bit line.
17. The semiconductor device of claim 13 , further including:
a refresh latch coupled to each bit line that stores a data value read from a corresponding storage cell coupled to the bit line; and
a sense block circuit coupled to the refresh latch that applies a potential to the bit line in a write operation according to the data value stored in the refresh latch.