Method for in-line monitoring of via/contact holes etch process based on test structures in semiconductor wafer manufacturing
A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations. Advanced process control (APC) can be performed in-line with the guidance of this image so that potential electrical defects are avoided and process yield ramp accelerated.
1. A device for characterizing an etching process, the device comprising:
an array of via regions formed by at least an etching process;
wherein the array of via regions includes:
a first via region associated with a first common via size and a first common via density;
a second via region associated with a second common via size and a second common via density;
a third via region associated with a third common via size and a third common via density;
a fourth via region associated with a fourth common via size and a fourth common via density;
wherein:
the first common via density is smaller than the second common via density;
the first common via density is equal to the third common via density;
the third common via density is smaller than the fourth common via density;
the second common via density is equal to the fourth common via density;
wherein:
the first common via size is equal to the second common via size;
the first common via size is smaller than the third common via size;
the third common via size is equal to the fourth common via size;
the second common via size is smaller than the fourth common via size.
2. The apparatus of claim 1 wherein the etching process is a single etching process to a first layer.
3. The apparatus of claim 2 wherein:
the array of via regions is located on a wafer;
the wafer includes at least a via outside the array of via regions;
the via is formed by performing the etching process to a second layer;
the first layer and the second layer are associated with a substantially same thickness and a substantially same composition.
4. The apparatus of claim 2 wherein the first layer is a dielectric layer.
5. The apparatus of claim 1 wherein:
the first via region is adjacent to the second via region;
the first via region is adjacent to the third via region;
the fourth via region is adjacent to the third via region;
the fourth via region is adjacent to the second via region.