Semiconductor device and method of manufacturing the same
View Patent ↗A semiconductor device and a method of manufacturing the same, wherein first and second gate electrodes are formed to have a spacer shape. The length of an underlying dielectric film can be automatically controlled. A gate oxide film and a third gate electrode are formed between the first and second gate electrodes. Voids are not generated when burying the third conductive film. A thickness and width of the gate oxide film can be freely controlled.
1. A method of manufacturing a semiconductor device, the method comprising the steps of:
forming a dielectric film on a semiconductor substrate and stripping the dielectric film of a predetermined region;
forming an interlayer insulating film on the region from which a portion of the dielectric film has been stripped;
forming a first conductive film on the entire structure, and blank etching the first conductive film to form first and second gate electrodes, which are insulated from the semiconductor substrate through the dielectric film, on sidewalls of the interlayer insulating film;
stripping the dielectric film exposed between the first and second gate electrodes;
forming an oxide film and a second conductive film on the entire structure, and then performing a blanket etch process to form a third gate electrode, which is insulated from the semiconductor substrate and the first and second gate electrodes by means of the oxide film between the first and second gate electrodes;
forming a third conductive film on the entire structure, and then performing a blanket etch process to form a fourth gate electrode connected to the first, second, and third gate electrodes; and
stripping the interlayer insulating film and then forming a source and drain at given regions of the semiconductor substrate.
2. The method of claim 1 , comprising forming the interlayer insulating film using an oxide film or a SiO x N y -based material.
3. The method of claim 1 , comprising depositing the first conductive film to have a thickness of ⅕ to ½ of a width of a buried region.
4. The method of claim 1 , comprising forming the first, second, third, and fourth gate electrodes using a member selected from the group consisting of doped polysilicon films, Al, W, WSi x , CoSi x , WN x , TiSi x , Ti, Ta, TaN, Ru, Pt, and mixtures thereof.