IP Library Granted Patent US 7,170,264
Granted Patent B1
US 7,170,264 · App. 11/456,432 · Granted Jan 30, 2007

Frequency compensation scheme for a switching regulator using external zero

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Quick Facts
Patent No.
US 7,170,264
App. No.
11/456,432
Granted
Jan 30, 2007
Kind
B1
Abstract

A compensation circuit in a monolithic switching regulator controller being incorporated in a closed loop feedback system of a switching regulator includes an amplifier configured in a unity gain feedback configuration with a first resistor and including a non-inverting input terminal receiving the feedback voltage and an inverting input terminal coupled to a first terminal of the switching regulator controller. The compensation circuit further includes a first capacitor and a third resistor connected in series between an input terminal and an output terminal of an error amplifier of the switching regulator controller. The first capacitor and the third resistor introduce a first zero in the closed loop feedback system. When a second capacitor is coupled to the first terminal of the switching regulator controller, a second zero is introduced in the closed loop feedback system. The second capacitor is an off-chip capacitor formed external to the monolithic switching regulator controller.

Claims (35)

1. A compensation circuit in a monolithic switching regulator controller being incorporated in a closed loop feedback system of a switching regulator, the switching regulator controller including an input terminal receiving an input voltage, an output terminal providing a switching output voltage corresponding to a regulated output voltage, a feedback terminal for receiving a feedback voltage corresponding to the regulated output voltage, and an error amplifier comparing a signal indicative of the feedback voltage and a reference voltage and generating an error output voltage, the compensation circuit comprising:

an amplifier including a non-inverting input terminal coupled to the feedback terminal for receiving the feedback voltage, an inverting input terminal coupled to a first terminal of the switching regulator controller, and an output terminal;

a first resistor connected between the inverting input terminal and the output terminal of the amplifier;

a second resistor connected between the output terminal of the amplifier and a first input terminal of the error amplifier, the first input terminal receiving the signal indicative of the feedback voltage; and

a first capacitor and a third resistor connected in series between the first input terminal and an output terminal of the error amplifier, the output terminal of the error amplifier providing the error output voltage,

wherein the first capacitor and the third resistor operate to introduce a first zero in the closed loop feedback system.

2. The compensation circuit of claim 1 , wherein a second capacitor is to be coupled to the first terminal of the switching regulator controller to introduce a second zero in the closed loop feedback system, the second capacitor being an off-chip capacitor formed external to the monolithic switching regulator controller.

3. The compensation circuit of claim 1 , wherein the output terminal of the switching regulator controller is coupled to an output filter circuit for generating the regulated output voltage, the output filter circuit comprising an inductor and a third capacitor connected in series between the output terminal of the switching regulator controller and a ground potential, wherein the third capacitor comprises a capacitor with a high equivalent series resistance (ESR).

4. The compensation circuit of claim 3 , wherein the third capacitor comprises a tantalum capacitor or an electrolytic capacitor.

5. The compensation circuit of claim 2 , wherein the output terminal of the switching regulator controller is coupled to an output filter circuit for generating the regulated output voltage, the output filter circuit comprising an inductor and a third capacitor connected in series between the output terminal of the switching regulator controller and a ground potential, wherein the third capacitor comprises a capacitor with a low equivalent series resistance (ESR).

6. The compensation circuit of claim 5 , wherein the third capacitor comprises a ceramic capacitor.

7. The compensation circuit of claim 5 , wherein the capacitance of the second capacitor is selected in accordance with the inductance of the inductor and the capacitance of the third capacitor of the output filter circuit.

8. The compensation circuit of claim 7 , wherein when the inductance of the inductor and the capacitance of the third capacitor of the output filter circuit have large values, the capacitance of the second capacitor increases correspondingly to decrease the frequency of the second zero; and when the inductance of the inductor and the capacitance of the third capacitor of the output filter circuit have small values, the capacitance of the second capacitor decreases correspondingly to increase the frequency of the second zero.

9. The compensation circuit of claim 2 , wherein a fourth resistor is to be coupled in parallel with the second capacitor to increase the gain of the closed loop feedback system.

10. The compensation circuit of claim 2 , wherein a fourth capacitor and a fourth resistor, connected in series, are to be coupled in parallel with the second capacitor to increase the gain of the closed loop feedback system at a frequency determined by the capacitance of the fourth capacitor and the resistance of the fourth resistor.

11. A method for providing zero compensation in a monolithic switching regulator controller being incorporated in a closed loop feedback system of a switching regulator receiving an input voltage and providing a regulated output voltage, the method comprising:

providing an amplifier in the switching regulator controller configured in a unity gain configuration including a first resistor connected between an inverting input terminal and an output terminal of the amplifier;

receiving a feedback voltage at a non-inverting input terminal of the amplifier, the feedback voltage corresponding to the regulated output voltage;

providing a second resistor between the output terminal of the amplifier and a first input terminal of an error amplifier of the switching regulator controller, the first input terminal of the error amplifier receiving a signal indicative of the feedback voltage; and

providing a first capacitor and a third resistor connected between the first input terminal and an output terminal of the error amplifier, the first capacitor and the third resistor introducing a first zero in the closed loop feedback system of the switching regulator.

12. The method of claim 11 , further comprising:

coupling the inverting input terminal of the amplifier to a first terminal of the switching regulator controller; and

coupling a second capacitor to the first terminal of the switching regulator controller to introduce a second zero in the closed loop feedback system, the second capacitor being an off-chip capacitor formed external to the monolithic switching regulator controller.

13. The method of claim 11 , further comprising:

coupling an output filter circuit to the switching regulator controller to generate the regulated output voltage, the output filter circuit comprising an inductor and a third capacitor being a capacitor with a high equivalent series resistance (ESR).

14. The method of claim 13 , wherein the third capacitor comprises a tantalum capacitor or an electrolytic capacitor.

15. The method of claim 12 , further comprising:

coupling an output filter circuit to the switching regulator controller to generate the regulated output voltage, the output filter circuit comprising an inductor and a third capacitor being a capacitor with a low equivalent series resistance (ESR).

16. The method of claim 15 , wherein the third capacitor comprises a ceramic capacitor.

17. The method of claim 15 , wherein the capacitance of the second capacitor is selected in accordance with the inductance of the inductor and the capacitance of the third capacitor of the output filter circuit.

18. The method of claim 17 , wherein when the inductance of the inductor and the capacitance of the third capacitor of the output filter circuit have large values, the capacitance of the second capacitor increases correspondingly to decrease the frequency of the second zero; and when the inductance of the inductor and the capacitance of the third capacitor of the output filter circuit have small values, the capacitance of the second capacitor decreases correspondingly to increase the frequency of the second zero.

19. The method of claim 12 , further comprising:

coupling a fourth resistor in parallel with the second capacitor to increase the gain of the closed loop feedback system.

20. The method of claim 12 , further comprising:

coupling a fourth capacitor and a fourth resistor, connected in series, in parallel with the second capacitor to increase the gain of the closed loop feedback system at a frequency determined by the capacitance of the fourth capacitor and the resistance of the fourth resistor.

Assignments (10)
INTELLECTUAL PROPERTY BUY-IN AGREEMENT/ASSIGNMENT Recorded Apr 4, 2023
From: MICREL LLC
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 063241/0771 →
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2006
From: GALINSKI, III, MARTIN F.
To: MICREL INC.
Reel/Frame 017905/0422 →