Virtual power rails for integrated circuits
View Patent ↗Methods and apparatuses to decrease power consumption and reduce leakage current of integrated circuits are disclosed. New leakage power saving techniques for various types of integrated circuits, including cache memory circuits, are discussed. Embodiments comprise methods and apparatuses to reduce power consumption in integrated circuits by using virtual voltage rails, or virtual power rails, to supply power to integrated circuit loads. The methods and apparatuses generally involve using one or two virtual power control devices to “head” and “foot”, or sandwich, the integrated circuit loads from firm power supply rails. In these method embodiments, one or more elements sense the voltage of the virtual power rails, or nodes, and make adjustments to control the voltage at certain “virtual” voltage potentials. While controlling the voltage in this manner, the virtual power control devices may serve to restrict unnecessary current flow through the integrated circuit loads.
1. A method to reduce leakage current of an integrated circuit load, the method comprising:
applying a first voltage to a first terminal of a single low potential device to create a low voltage at a low voltage node, wherein a second terminal and a third terminal of the single low potential device are coupled to the low voltage node,
controlling the low voltage by the single low potential device, wherein the single low potential device senses the low voltage via the third terminal to control the low voltage, wherein further the single low potential device comprises a single-gate device;
applying a second voltage to a high supply node, wherein the high supply node is coupled to the integrated circuit load; and
supplying power to the integrated circuit load via the first voltage and the second voltage.
2. The method of claim 1 , further comprising controlling a high voltage of a high voltage node by a single high potential device, wherein the single high potential device is coupled to the high supply node via a fourth terminal and coupled to the high voltage node via a fifth terminal and a sixth terminal.
3. The method of claim 2 , wherein controlling the high voltage of the high voltage node by the single high potential device comprises operating a single p-type transistor in a near cutoff state to control the high voltage, wherein further the single p-type transistor comprises a single-gate transistor.
4. The method of claim 1 , wherein controlling the low voltage by the single low potential device comprises continually operating a single n-type transistor in a near cutoff state to control the low voltage.
5. The method of claim 1 , wherein generating a first voltage and generating a second voltage comprise creating virtual power rails for a plurality of SRAM circuits.
6. An apparatus to reduce leakage current in an integrated circuit, the apparatus comprising:
at least one load of the integrated circuit coupled to a first node and a second node;
a first lone transistor coupled to the first node and to a first voltage source, wherein the first lone transistor comprises a single-gate n-FET adapted to sense a low voltage of the first node and control the low voltage based on the sensing, wherein further the low voltage is to be positive relative to the first voltage source, wherein the n-FET source terminal is coupled to the first voltage source and the n-FET gate terminal and the n-FET drain terminal are coupled to the first node; and
a second voltage source coupled to the second node, wherein the second node is to be at a high voltage when the integrated circuit is operated, wherein further the high voltage is to be positive relative to the low voltage.
7. The apparatus of claim 6 , further comprising a second circuit device coupled to the second node and to the second voltage source, wherein the second circuit device is adapted to control the high voltage.
8. The apparatus of claim 7 , wherein the second circuit device comprises a p-FET with a p-FET drain coupled to the second voltage source and with a p-FET gate and a p-FET source coupled to the second node.
9. The apparatus of claim 8 , wherein the at least one load comprises at least one SRAM memory device.
10. The apparatus of claim 9 , wherein the at least one SRAM memory device comprises at least one 6T-SRAM cell.
11. The apparatus of claim 8 , wherein the first voltage source comprises a power supply Vss and the second voltage source comprises the power supply Vdd.
12. The apparatus of claim 8 , wherein the single-gate n-FET and the p-FET are configured to symmetrically set the power level of the at least one load to a middle power level VDD/2.
13. A system, comprising:
a power supply;
a virtual power device coupled to a supply voltage node of the power supply, wherein the virtual power device comprises a singular transistor arranged to provide a supply voltage for a virtual supply node, wherein further the singular transistor comprises a single-gate transistor;
at least one electrical load coupled to the virtual supply node and a virtual ground node; and
a virtual ground device coupled to the virtual ground node and to a ground node of the power supply, wherein the virtual ground device comprises a second singular transistor arranged to sense a low voltage of the virtual ground node and control the low voltage based on the sensing, wherein further the second singular transistor comprises a second single-gate transistor.
14. The system of claim 13 , wherein the virtual power device is a p-MOS transistor with the drain terminal of the p-MOS transistor coupled to the supply voltage node and with the gate terminal and the source terminal of the p-MOS transistor coupled to the virtual supply node, wherein further the virtual ground device is an n-MOS transistor with the gate terminal and the drain terminal of the n-MOS transistor coupled to the virtual ground node and with the source terminal of the n-MOS transistor coupled to the ground node.
15. The system of claim 13 , wherein the at least one electrical load comprises one of SRAM memory, cache memory, integrated circuit logic gates, and digital signal processing circuitry.
16. The system of claim 13 , wherein the system comprises one of a cellular telephone, a portable computing device, a desktop computer, and a rack-mount computing device.
17. A computer program product comprising a computer usable medium having computer usable program code for creating an integrated circuit, the computer program product including;
computer usable program code for creating an integrated circuit load;
computer usable program code for coupling a first virtual potential device to the integrated circuit load, wherein the first potential device comprises a singular transistor adapted to monitor and control a first voltage to be supplied to the integrated circuit load, wherein further the singular transistor comprises a single-gate transistor;
computer usable program code for coupling the first virtual potential device to a first conductor; and
computer usable program code for coupling the integrated circuit load to a second conductor, wherein the first conductor and the second conductor are to be coupled to a power supply.
18. The computer program product of claim 17 , further comprising computer usable program code for coupling a second virtual potential device to the integrated circuit load and to the second conductor, wherein the second virtual potential device is adapted to monitor and control a second voltage to be supplied to the integrated circuit load.
19. The computer program product of claim 18 , wherein the computer usable program code for coupling the second virtual potential device to the integrated circuit load comprises computer usable program code for forming an n-MOS transistor with a gate and a source coupled to the integrated circuit and a drain coupled to the second conductor.
20. The computer program product of claim 17 , wherein the computer usable program code for creating an integrated circuit load comprises computer usable program code for forming at least one cache memory device.