IP Library Granted Patent US 7,800,879
Granted Patent B2
US 7,800,879 · App. 11/460,459 · Granted Sep 21, 2010

On-chip sensor array for temperature management in integrated circuits

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Quick Facts
Patent No.
US 7,800,879
App. No.
11/460,459
Granted
Sep 21, 2010
Kind
B2
Abstract

Embodiments of the invention provide methods and apparatus for managing temperature in integrated circuits. In accordance with an aspect of the invention, an integrated circuit comprises a monitored region defined by three or more edges. What is more, the integrated circuit comprises at least two temperature sensors for each of the three or more edges. The temperature sensors are arranged along the three or more edges such that each edge has substantially the same arrangement of temperature sensors. Thermal management of the integrated circuit may be accomplished by modifying functional aspects of the integrated circuit in response to measurements provided by the temperature sensors.

Claims (36)

1. An integrated circuit comprising:

a monitored region, the monitored region defined by three or more edges; and

at least two temperature sensors for each of the three or more edges, the temperature sensors being arranged along the three or more edges such that each edge has substantially the same arrangement of temperature sensors;

wherein positional information of a thermal characteristic of the monitored region is deter ruined by combining an output of at least a first one of the temperature sensors at a first position along a first one of the edges with an output of at least a second one of the temperature sensors at a second position along a second one of the edges, said positional information denoting a position other than the first and second positions; and

wherein the position denoted by the positional information is not a position of any of the temperature sensors and is spaced a distance from each of the first and second positions which is greater than a distance between two adjacent ones of the temperature sensors arranged along a given one of the edges.

2. The integrated circuit of claim 1 , wherein the monitored region is substantially the entire integrated circuit.

3. The integrated circuit of claim 1 , wherein the plurality of temperature sensors allows the determination of power dissipation in the monitored region.

4. The integrated circuit of claim 3 , wherein the power dissipation can be determined with an uncertainty less than about ten percent.

5. The integrated circuit of claim 1 , wherein the plurality of temperature sensors allows the determination of a center of power dissipation for the monitored region.

6. The integrated circuit of claim 1 , wherein the monitored region is substantially a square defined by four edges.

7. The integrated circuit of claim 6 , wherein eight temperature sensors are arranged along the four edges of the monitored region with two of the eight temperature sensors arranged along each of the four edges.

8. The integrated circuit of claim 6 , wherein twelve temperature sensors are arranged along the four edges of the monitored region with three of the twelve temperature sensors arranged along each of the four edges.

9. The integrated circuit of claim 6 , wherein sixteen temperature sensors are arranged along the four edges of the monitored region with four of the sixteen temperature sensors arranged along each of the four edges.

10. An integrated circuit comprising:

a monitored region, the monitored region defined by three or more edges; and

at least two temperature sensors for each of the three or more edges, the temperature sensors being arranged along the three or more edges such that each edge has substantially the same arrangement of temperature sensors;

wherein the plurality of temperature sensors are arranged such that a first interior angle formed by a first set of two lines radiating from a center of the monitored region to respective ones of a first set of two adjacent temperature sensors is substantially equal to a second interior angle formed by a second set of two lines radiating from the center of the monitored region to respective ones of a second set of two adjacent temperature sensors.

11. The integrated circuit of claim 1 , wherein at least one of the plurality of temperature sensors comprises a semiconductor diode, a resistor element or an oscillator circuit.

12. The integrated circuit of claim 1 , wherein at least some signals produced by the temperature sensors are multiplexed.

13. A method of forming an integrated circuit, the method comprising the steps of:

forming a monitored region, the monitored region defined by three or more edges; and

forming at least two temperature sensors for each of the three or more edges, the temperature sensors being arranged along the three or more edges such that each edge has substantially the same arrangement of temperature sensors;

wherein positional information of a thermal characteristic of the monitored region is determined by combining an output of at least a first one of the temperature sensors at a first position along a first one of the edges with an output of at least a second one of the temperature sensors at a second position along a second one of the edges, said positional information denoting a position other than the first and second positions; and

wherein the position denoted by the positional information is not a position of any of the temperature sensors and is spaced a distance from each of the first and second positions which is greater than a distance between two adjacent ones of the temperature sensors arranged along a given one of the edges.

14. The method of claim 13 , wherein the temperature sensors are formed using complementary metal-oxide-semiconductor technology.

15. The method of claim 13 , wherein forming the plurality of temperature sensors does not require more processing steps than are required to form the remainder of the integrated circuit.

16. An integrated circuit comprising:

a monitored region, the monitored region defined by three or more edges;

at least two temperature sensors for each of the three or more edges, the temperature sensors being arranged along the three or more edges such that each edge has substantially the same arrangement of temperature sensors; and

control circuitry, the control circuitry at least operative to receive one or more signals from the plurality of temperature sensors, analyze the received signals to determine one or more thermal properties of the monitored region, and modify one or more functional aspects of the integrated circuit if the determined thermal properties fall outside a predetermined range;

wherein positional information of a thermal characteristic of the monitored region is determined by combining an output of at least a first one of the temperature sensors at a first position along a first one of the edges with an output of at least a second one of the temperature sensors at a second position along a second one of the edges, said positional information denoting a position other than the first and second positions; and

wherein the position denoted by the positional information is not a position of any of the temperature sensors and is spaced a distance from each of the first and second positions which is greater than a distance between two adjacent ones of the temperature sensors arranged along a given one of the edges.

17. The integrated circuit of claim 16 , wherein the control circuitry is operative to change one or more clock speeds in the integrated circuit.

18. The integrated circuit of claim 16 , wherein the control circuitry is operative to change one or more supply voltages in the integrated circuit.

19. The integrated circuit of claim 16 , wherein the control circuitry is operative to change one or more cooling mechanisms for the integrated circuit.

20. The integrated circuit of claim 16 , wherein the control circuitry is operative to reroute one or more processing tasks in the integrated circuit.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2006
From: RYAN, VIVIAN
To: AGERE SYSTEMS INC.
Reel/Frame 018013/0778 →