IP Library Granted Patent US 7,436,489
Granted Patent B2
US 7,436,489 · App. 11/460,630 · Granted Oct 14, 2008

Device for testing an exposure apparatus

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Quick Facts
Patent No.
US 7,436,489
App. No.
11/460,630
Granted
Oct 14, 2008
Kind
B2
Abstract

A device and a method for testing an exposure apparatus is disclosed. A testing device includes a substrate, and a plurality of block patterns, each of which has a top area varying with an area of a shot region of the exposure apparatus, having at least two different heights located on the substrate. Additionally, the method for testing an exposure apparatus includes using the exposure apparatus to perform an exposure process on the testing device or on the testing device having a photoresist layer thereon, and testing the performance of the exposure apparatus through comparing surface information of the testing device computed by the exposure apparatus with actual surface information of the testing device or through examining photoresist patterns formed on the testing device.

Claims (7)

1. A testing device for testing a calculation function of a surface topography detection system and a drive function of a wafer stage of an exposure apparatus comprising:

a substrate; and

a plurality of block patterns having at least two different heights positioned on the substrate in an identical level, each of the block patterns having a top area corresponding to an area of a shot region of the exposure apparatus, wherein the top areas of the block patterns corresponding to the areas of the shot regions are not different.

2. The testing device of claim 1 wherein the exposure apparatus is a step-and-scan exposure apparatus or a stepper.

3. The testing device of claim 2 further comprising a plurality of alignment marks positioned on the substrate and used in a wafer alignment step performed in the exposure apparatus.

4. The testing device of claim 1 wherein the substrate is made of a material selected from the group consisting of silicon, glass, and quartz.

5. The testing device of claim 1 wherein a relative height between two adjacent block patterns is between 0.05 μm and 0.5 μm.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049757/0575 →
CHANGE OF NAME Recorded Jun 26, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049602/0564 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2006
From: WANG, HUNG-CHI; LIN, WEI-FENG
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 018016/0309 →