SRAM having variable power supply and method therefor
View Patent ↗A memory circuit has a memory array with a first line of memory cells, a second line of memory cells, a first power supply terminal, a first capacitance structure, a first power supply line coupled to the first line of memory cells; and a second power supply line coupled to the second line of memory cells. For the case where the second line of memory cells is selected for writing, a switching circuit couples the power supply terminal to the first power supply line, decouples the first power supply line from the second line of memory cells, and couples the second power supply line to the first capacitance structure. The result is a reduction in power supply voltage to the selected line of memory cells by charge sharing with the capacitance structure. This provides more margin in the write operation on a cell in the selected line of memory cells.
1. A memory circuit, comprising:
a memory array comprising a first line of memory cells and a second line of memory cells;
a first power supply terminal;
a first capacitance structure includes a plurality of dummy cells;
a first power supply line coupled to the first line of memory cells;
a second power supply line coupled to the second line of memory cells; and
a switching circuit that has transistors that, connected between the first power supply terminal, the first power supply line, the second power supply line and the first capacitance structure wherein when the second line of memory cells is selected for writing, couple the first power supply terminal to the first power supply line, decouple the first power supply terminal from the second line of memory cells, and couple the second power supply line to the first capacitance structure.
2. The memory circuit of claim 1 , wherein the first line of memory cells comprises a first column of memory cells and the second line of memory cells comprises a second line of memory cells.
3. The memory circuit of claim 1 , wherein the first capacitance structure comprises:
a dummy line; and
the plurality of dummy cells coupled to the dummy line.
4. The memory circuit of claim 3 , further comprising a first dummy cell adjacent to but not coupled to the dummy line.
5. The memory circuit of claim 1 , wherein the first power supply terminal comprises a positive power supply terminal.
6. The memory circuit of claim 1 , wherein the switching circuit further comprises a switching transistor coupled between the capacitance structure and a voltage reference terminal.
7. The memory circuit of claim 6 , wherein the voltage reference terminal comprises a ground terminal.
8. The memory circuit of claim 1 , wherein the first line of memory cells comprises a first row of memory cells and the second line of memory cells comprises a second row of memory cells.
9. The memory of claim 1 , further comprising:
a second power supply terminal;
a third line of memory cells intersecting the first and second line of memory cells;
a fourth line of memory cells intersecting the first and second line of memory cells;
a second capacitance structure;
a third power supply line coupled to the third line of memory cells; and
a fourth power supply line coupled to the fourth line of memory cells; wherein
the switching circuit further comprising transistors that, when the fourth line of memory cells is selected for writing, couple the second power supply terminal to the third power supply line, decouple the second power supply terminal from the fourth line of memory cells, and couple the fourth power supply line to the second capacitance structure.
10. The memory circuit of claim 9 , wherein:
the first and second lines of memory cells comprise columns;
the third and fourth lines of memory cells comprise rows;
the first power supply terminal comprises a positive power supply terminal;
the second power supply terminal comprises a negative power supply terminal;
the first capacitance structure comprises a first line and a first plurality of dummy cells coupled to the first line; and
the second capacitance structure comprises a second line and a second plurality of dummy cells coupled to the second line.
11. The memory circuit of claim 1 , further comprising a voltage clamp coupled between the first power supply terminal and the first power supply line.
12. A method, comprising:
providing a memory comprising:
a memory array comprising a first line of memory cells and a second line of memory cells;
a first power supply terminal;
a first capacitance structure includes a plurality of dummy cells;
a first power supply line coupled to the first line of memory cells; and
a second power supply line coupled to the second line of memory cells;
a switching circuit that has transistors that connected between the first power supply terminal, the first power supply line, the second power supply line and the first capacitance structure
selecting the second line of memory cells for writing;
coupling the first power supply terminal to the first power supply line;
decoupling the second line of memory cells from the first power supply terminal;
coupling charge from the second power supply line to the first capacitance structure; and
writing a memory cell in the second line of memory cells.
13. The method of claim 12 further comprising precharging the first capacitance structure prior to the step of coupling charge.
14. The method of claim 13 , wherein the step of precharging is further characterized as precharging the first capacitance structure to ground.
15. The method of claim 13 , wherein the step of precharging is further characterized by precharging the first capacitance structure to a voltage present on the first power supply terminal.
16. The memory circuit of claim 12 , further comprising preventing the step of coupling charge from reducing a voltage on the second power supply line to a level below a predetermined voltage.
17. A memory circuit, comprising:
a memory array comprising a first line of memory cells and a second line of memory cells;
a power supply terminal;
a capacitance structure;
a first power supply line coupled to the first line of memory cells;
a second power supply line coupled to the second line of memory cells;
precharging means for precharging the capacitance structure to a predetermined voltage prior to a write operation for the second line of memory cells;
first coupling means for coupling the power supply terminal to the first power supply line during the write operation for the second line of memory cells;
decoupling means for decoupling the first power supply line from the second line of memory cells during the write operation for the second line of memory cells; and
second coupling means for coupling the second supply line to the first capacitance structure during the write operation for the second line of memory cells.
18. The memory circuit of claim 17 wherein the predetermined voltage comprises one of a group consisting of a positive power supply voltage and ground.
19. The memory circuit of claim 18 , wherein the capacitance structure comprises:
a dummy line;
a plurality of dummy cells adjacent to and coupled to the dummy line; and
a first dummy cell adjacent to but not coupled to the dummy line.
20. The memory circuit of claim 17 , wherein the first line of memory cells comprises one of a group consisting of a row and a column.