Semiconductor device
View Patent ↗A semiconductor device is disclosed which can perform a stable data inputting operation by overdriving a terminal supplying an internal voltage used as a drive voltage for a write driver such that the internal voltage is maintained in a predetermined range irrespective of a continuous write operation. The semiconductor device includes an internal voltage generator which generates an internal voltage corresponding to a predetermined reference voltage, and outputs the generated internal voltage to an internal voltage supply terminal, an overdriver which overdrives the internal voltage supply terminal for a predetermined period of time in response to an enable state of a control signal, the control signal being enabled in a write operation, and a write driver which is enabled in response to the control signal, to drive data transferred via a global data bus line using a voltage supplied from the internal voltage supply terminal, and to output the driven data to a local data bus line.
1. A semiconductor device comprising:
an internal voltage generator which generates an internal voltage corresponding to a predetermined reference voltage, and outputs the generated internal voltage to an internal voltage supply terminal;
a signal generator which generates an overdrive enable signal in response to a control signal, the control signal being enabled in a write operation;
a pull-up driver which pulls up the internal voltage supply terminal using an external voltage in response to the overdrive enable signal; and
a write driver which is enabled in response to the control signal, to drive data transferred via a global data bus line using a voltage supplied from the internal voltage supply terminal, and to output the driven data to a local data bus line,
wherein the overdrive enable signal is enabled signal when the control signal transits to a enable state, the overdrive enable signal is disabled when the delay time elapses after the control signal transits to a disable state.
2. The semiconductor device according to claim 1 , wherein the control signal is a write enable signal.
3. The semiconductor device according to claim 1 , wherein the internal voltage is a core voltage of the semiconductor device.
4. The semiconductor device according to claim 1 , wherein the pull-up driver includes a plurality of pull-up devices which are connected in parallel between an external voltage supply terminal and the internal voltage supply terminal.
5. The semiconductor device according to claim 4 , wherein the pull-up driver further includes a plurality of control switches, a part of the pull-up devices being controlled to be turned on/off by the control switches.
6. The semiconductor device according to claim 1 , wherein the signal generator includes:
a delay which delays the control signal for a predetermined delay time; and
a logic unit which logically operates the control signal and a signal output from the delay, and outputs a result of the logical operation.
7. The semiconductor device according to claim 3 , wherein the logic unit performs an ANDing operation.
8. The semiconductor device according to claim 6 , wherein the logic unit performs a NANDing operation.
9. The semiconductor device according to claim 6 , wherein the delay includes a plurality of delay elements and a plurality of control switches, and controls the delay time in accordance with operations of the control switches.
10. The semiconductor device according to claim 9 , wherein the delay includes:
a first delay which is connected between a first node and a second node;
a first switch which is connected between the first node and the second node in parallel to the first delay; and
a second delay which delays a signal from the second node.
11. The semiconductor device according to claim 1 , wherein the signal generator includes:
a buffer which buffers the control signal;
a delay which delays a signal output from the buffer for a predetermined delay time; and
a logic unit which logically operates the output signal from the buffer and a signal output from the delay, and outputs a result of the logical operation.
12. The semiconductor device according to claim 11 , wherein the logic unit performs a NANDing operation
13. The semiconductor device according to claim 11 , wherein the logic unit performs an ANDing operation.
14. The semiconductor device according to claim 11 , wherein the delay includes a plurality of delay elements and a plurality of control switches, and controls the delay time in accordance with operations of the control switches.
15. The semiconductor device according to claim 14 , wherein the delay includes:
a first delay which is connected between a first node and a second node;
a first switch which is connected between the first node and the second node in parallel to the first delay; and
a second delay which delays a signal from the second node.
16. The semiconductor device according to claim 1 , wherein the internal voltage generator includes:
a comparator which compares the internal voltage with the reference voltage in response to an internal voltage enable signal, and outputs a first enable signal in accordance with a result of the comparison; and
an internal voltage driver which pulls up the internal voltage to a level of an external voltage in response to the first enable signal.
17. The semiconductor device according to claim 16 , further comprising:
a comparator enabling unit which receives the internal voltage enable signal, and enables the comparator in response to the received internal voltage enable signal.
18. The semiconductor device according to claim 17 , wherein the comparator enabling unit includes:
a pull-up device which outputs the comparator enable signal when the internal voltage enable signal is enabled; and
a pull-down device which outputs a disable signal to disable the comparator when the internal voltage enable signal is disabled.
19. The semiconductor device according to claim 16 , wherein the comparator includes:
a first pull-up device which is connected between an external voltage supply terminal and a first node;
a second pull-up device which is connected between the external voltage supply terminal and a second node;
a first pull-down device which is connected between the first node and a ground terminal, to receive, as a drive voltage, the reference voltage at a gate of the first pull-down device; and
a second pull-down device which is connected between the second node and the ground terminal, to receive, as a drive voltage, the internal voltage at a gate of the second pull-down device.
20. The semiconductor device according to claim 19 , further comprising:
a comparator enabling unit which receives the internal voltage enable signal, and enables the comparator in response to the received internal voltage enable signal.
21. The semiconductor device according to claim 20 , wherein the comparator enabling unit includes:
a pull-up device which outputs the comparator enable signal when the internal voltage enable signal is enabled; and
a pull-down device which outputs a disable signal to disable the comparator when the internal voltage enable signal is disabled.
22. The semiconductor device according to claim 1 , wherein the write driver includes:
a data transfer unit which drives the data transferred via the global data bus line to a level of the voltage supplied from the internal voltage supply terminal, and outputs the driven data;
a logic unit which logically operates the control signal enabled in the write operation and a predetermined pre-charge signal; and
a pre-charging unit which pre-charges the local data bus line in response to a signal output from the logic unit.
23. The semiconductor device according to claim 22 , wherein the logic unit performs an ANDing operation.
24. The semiconductor device according to claim 22 , wherein the logic unit performs a NANDing operation.