Granted Patent B2

US 7,668,029 · App. 11/464,124 · Granted Feb 23, 2010

Abstract

Claims (25)

1. A method for accessing a memory array, the method comprising:

beginning a bit line precharge operation based on a clock edge of an external clock signal, wherein the clock edge comprises one of a group consisting of a logic low to logic high transition and a logic high to logic low transition;

terminating the bit line precharge operation a first predetermined duration after the clock edge that is independent of a clock period of the external clock signal;

enabling a word line after the terminating of the bit line precharge operation;

beginning a sense operation after the enabling the word line, the sense operation for sensing a logic state of a memory cell; and

outputting a data bit from the memory array corresponding to the sensed logic state of the memory cell;

wherein:

the method is characterized as being self-timed from the step of beginning the bit line precharge to the step of beginning the sense operation and based on the clock edge of the external clock signal; and

the step of beginning the sense operation is further characterized by beginning a second predetermined duration after the step of enabling the word line begins and by the sense operation having a variable duration.

2. The method of claim 1 further comprising implementing the memory as a static random access memory (SRAM).

3. The method of claim 1 , wherein the variable duration is dependent, at least in part, on a clock period of the external clock signal.

4. The method of claim 1 , wherein the step of beginning a sense operation further comprises beginning a sense operation using a static sense amplifier.

5. The method of claim 1 , wherein the memory array is a read/write memory array.

6. A method comprising:

providing a memory array having a plurality of memory cells, a memory cell of the plurality of memory cells located at intersections of intersecting bit lines and word lines;

providing an address to access a memory cell of the plurality of memory cells;

beginning a bit line precharge operation, the bit line precharge operation based on a clock edge of an external clock signal, the bit line precharge operation having a predetermined duration independent of a clock period of the external clock signal;

enabling a word line a first predetermined delay after the beginning of the bit line precharge operation;

beginning a sense operation on the memory cell for accessing at the address provided in the step of providing the address a second predetermined delay after the enabling the word line, the sense operation having a duration based on the clock period of the external clock signal;

outputting a data bit from the memory array, the data bit corresponding to a logic state of the memory cell sensed during the sense operations; and

terminating the sense operation after a predetermined time if termination of the clock period has not occurred prior to the predetermined time.

7. The method of claim 6 , wherein the step of providing the memory array is further characterized by providing a plurality of static random access memory (SRAM) cells.

8. The method of claim 6 , wherein the step of beginning the sense operation further comprises beginning a sense operation using a static sense amplifier.

9. The method of claim 6 , wherein the duration increases as the clock period increases.

10. The method of claim 6 , wherein the step of outputting the data bit further comprises outputting a data bit within a clock period following the clock edge of the external clock signal.

Assignments (27)