IP Library Granted Patent US 7,966,379
Granted Patent B2
US 7,966,379 · App. 11/469,267 · Granted Jun 21, 2011

In-band event polling

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,966,379
App. No.
11/469,267
Granted
Jun 21, 2011
Kind
B2
Abstract

In-band event polling mechanism. A master device may initiate a polling transaction to poll at least a subset of a plurality of slave devices for event information. In response to the polling transaction, at least one of the subset of slave devices may transmit event information to the master device. The event information may correspond to at least one of a plurality of asynchronous event types. If the event type associated with the received event information is an event notification for an embedded processor of the master device, the master device may forward the event information to the embedded processor. Otherwise, if the event type associated with the received event information is an event notification for a device external to the master device (e.g., a host processor), the master device may translate the event information to a protocol associated with the event type and forward the event information to the external device.

Claims (44)

1. A computer system comprising:

a first bus;

a plurality of slave devices coupled to the first bus; and

a master device comprising an event polling controller and an embedded processor, and coupled to the first bus, and configured to initiate a polling transaction over the first bus to poll at least a subset of the plurality of slave devices for event information used for conveying a plurality of distinct asynchronous event types;

wherein, in response to the polling transaction, at least one of the at least a subset of the plurality of slave devices is configured to transmit first event information to the master device over the first bus, wherein the first event information corresponds to a first event type of the plurality of distinct asynchronous event types, and indicates an associated asynchronous event of the first event type in the at least one of the at least a subset of the plurality of slave devices;

wherein the master device is configured to receive the first event information from the at least one of the at least a subset of the plurality of slave devices over the first bus, and determine where to forward the received first event information based on the first event type, wherein if the first event type is an event notification for the embedded processor, the event polling controller is configured to forward the received first event information to the embedded processor;

wherein the first bus is configured to carry synchronous data transactions between the master device and the at least a subset of the plurality of slave devices.

2. The computer system of claim 1 , wherein if the first event type is an event notification for a device external to the master device, the master device is configured to translate the received first event information to a protocol associated with the event type and forward the first event information to the external device.

3. The computer system of claim 1 , wherein if the first event type is a SIRQ, the master device is configured to translate the received first event information to a protocol associated with SIRQ and forward the first event information to a device external to the master device.

4. The computer system of claim 1 , wherein if the first event type is a DMA request, the master device is configured to translate the received first event information to a protocol associated with DMA and forward the first event information to a device external to the master device.

5. The computer system of claim 1 , wherein the master device includes a mapping mechanism configured to read the received first event information and determine the first event type, wherein the master device is configured to forward the received first event information to one or more destinations based on the first event type.

6. The computer system of claim 1 , wherein the received first event information includes mapping information indicative of the first event type, wherein the master device is configured to read the mapping information to determine the first event type and also determine where to forward the received first event information.

7. The computer system of claim 1 , wherein the received first event information includes a plurality of data bits, wherein the plurality of data bits correspond to one or more of the plurality of distinct asynchronous event types, wherein the forwarding of a particular bit or a particular subset of bits to a particular destination is independent of the forwarding of another bit or another subset of bits.

8. The computer system of claim 1 , wherein the first bus has a reduced pin count relative to an LPC (Low Pin Count) bus.

9. The computer system of claim 8 , further comprising a second bus and a host processor, wherein if the first event type is an event notification for the host processor, the master device is configured to translate and forward the first event information to the host processor via the second bus.

10. The computer system of claim 9 , wherein the second bus is an LPC bus.

11. The computer system of claim 1 , wherein the plurality of slave devices are configured to transmit event information corresponding to the plurality of distinct asynchronous event types to the master device via a single bus and a single protocol.

12. The computer system of claim 1 , wherein the rate at which the master device polls the at least a subset of the plurality of slave devices is programmable.

13. A method for event polling in a system including a master device coupled to a plurality of slave devices by a first bus, the method comprising:

sending synchronous data transactions between the master device and one or more of the plurality of slave devices over the first bus;

the master device polling at least a subset of the plurality of slave devices over the first bus for event information used for conveying a plurality of distinct asynchronous event types;

in response to said polling, at least one of the at least one of the subset of the plurality of slave devices transmitting first event information to the master device over the first bus, wherein the first event information corresponds to a first event type of the plurality of distinct asynchronous event types, and indicates an associated asynchronous event of the first event type in the at least one of the at least a subset of the plurality of slave devices;

the master device receiving the first event information transmitted by the at least one of the at least a subset of the plurality of slave devices over the first bus;

the master device determining where to forward the received first event information based on the first event type; and

the master device forwarding the received first event information to an embedded processor within the master device, if the first event type is an event notification for the embedded processor.

14. The method of claim 13 , wherein if the first event type is a SIRQ, the master device translating the received first event information to a protocol associated with SIRQ and forwarding the first event information to a device external to the master device.

15. The method of claim 13 , wherein if the first event type associated with the received event information is a DMA request, translating the received first event information to a protocol associated with DMA and forwarding the first event information to a device external to the master device.

16. A master device comprising:

an embedded processor;

a transmission mechanism configured to initiate a polling transaction to poll at least a subset of a plurality of slave devices over a first bus for event information used for conveying a plurality of distinct asynchronous event types, and further configured to send synchronous data transactions to one or more of the plurality of slave devices over the first bus; and

an event polling controller configured to receive first event information transmitted by at least one of the at least a subset of the plurality of slave devices over the first bus in response to being polled for event information, wherein the first event information corresponds to a first event type of the plurality of distinct asynchronous event types, and indicates an associated asynchronous event of the first event type in the at least one of the at least a subset of the plurality of slave devices;

wherein the event polling controller is configured to determine where to forward the received first event information based on the first event type; and

wherein if the first event type is an event notification for the embedded processor, the event polling controller is configured to forward the received first event information to the embedded processor.

17. A computer system comprising:

a host processor;

a low pin count (LPC) bus coupled to a logic chipset;

a master device coupled to the LPC bus and comprising an embedded processor;

a second bus coupled to the master device, wherein the second bus has a reduced pin count relative to the LPC bus; and

a plurality of slave devices coupled to the second bus;

wherein the master device is configured to initiate a polling transaction to poll at least a subset of the plurality of slave devices for event information used for conveying a plurality of distinct asynchronous event types via the second bus, and is further configured to send synchronous data transactions to one or more of the plurality of slave devices over the second bus;

wherein, in response to the polling transaction, at least one of the at least a subset of the plurality of slave devices is configured to transmit first event information to the master device via the second bus, wherein the first event information corresponds to a first event type of the plurality of distinct asynchronous event types, and indicates an associated asynchronous event of the first event type in the at least one of the at least a subset of the plurality of slave devices;

wherein the master device is configured to receive the first event information from the at least one of the at least a subset of the plurality of slave devices and determine where to forward the received first event information based on the first event type;

wherein if the first event type is an event notification for the embedded processor of the master device, the master device is configured to forward the received first event information to the embedded processor; and

wherein if the first event type is an event notification for the host processor of the computer system, the master device is configured to translate the received first event information to a protocol associated with the first event type and forward the first event information to the host processor.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
MERGER Recorded Dec 11, 2017
From: STANDARD MICROSYSTEMS CORPORATION
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 044824/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 1, 2006
From: BERENBAUM, ALAN D.; WEISS, RAPHAEL
To: STANDARD MICROSYSTEMS CORPORATION
Reel/Frame 018198/0008 →