Computer processor capable of responding with comparable efficiency to both software-state-independent and state-dependent events
View Patent ↗A technique for enabling a computer processor to be capable of responding with comparable efficiency to both: (i) events whose handling is independent on the state of the software machine that responds to the events, and (ii) events whose handling is dependent on the state of the software machine that responds to the events. Each time a software state machine enters a state, one or more event control registers are programmed to direct the illustrative embodiment where to resume execution when each possible event occurs. This enables the illustrative embodiment to automatically branch to the code that is appropriate for the combination of the event and the state of the software machine.
1. A processor comprising:
an activation controller;
a pluralilty of hardware contexts, each of the hardware contexts associated with a predetermined first event and a predetermined second event and comprising:
(1) a program counter that stores a first memory address;
(2) a first programmable event control register associated with a first event, the first programmable event control register programmed to designate that a first sum of the first memory address and a first offset is to be stored in the program counter when said first event occurs;
(3) a second programmable event control register associated with a second event, the second programmable event control register programmed to designate that a second sum of the first memory address and a second offset is to be stored in the program counter when said second event occurs; and
(4) the activation controller for responding to said first event and said second event by:
(4.1) respectively storing the first sum and the second sum into said program counter when said first event and said second event occurs.
2. The processor of claim 1 wherein said activation controller is also for (4.2) ignoring said first event when said programmable event control register is programmed to ignore said first event.
3. A processor comprising:
an activation controller;
a context controller for controlling the processor between multiple hardware contexts; and
a plurality of hardware contexts, each of the plurality of hardware contexts comprising:
(1) a program counter that stores a first memory address and a second memory address;
(2) a first programmable event control register associated with a first event and a second programmable event control register associated with a second event; and
(3) the activation controller responding to said event by:
(3.1) leaving said first memory address unmodified when said programmable event control register is programmed to leave said first memory address unmodified when said first event occurs,
(3.2) storing a first sum of a second memory address plus a first offset into said program counter when said first programmable event control register is programmed to store a sum of the first memory address plus said first offset when said first event occurs, and
(3.3) storing the second sum into said program counter when said second programmable event control register is programmed to store the second sum when said second event occurs.
4. The processor of claim 3 wherein said activation controller is also for storing a sum of said first memory address plus a third offset into said program counter when said first programmable event control register is programmed to store the sum of said first memory address plus said third offset into said program counter when said first event occurs.
5. The processor of claim 3 wherein said activation controller is also for (3.4) ignoring said first event when said first programmable event control register is programmed to ignore said first event.
6. A processor comprising:
a context controller for controlling the processor between multiple hardware contexts;
an activation controller; and
a plurality of hardware contexts, each of the plurality of hardware contexts comprising:
(1) a program counter that stores a first memory address;
(2) a first programmable event control register associated with a first event; and
(3) a second programmable event control register associated with a second event,
(4) the activation controller responding to said first event and said second event by:
(4.1) storing the sum of said first memory address plus a first offset into said program counter when said first programmable event control register is programmed to store the sum of said first memory address plus said first offset into said program counter when said first event occurs, and
(4.2) storing the sum of said first memory address plus a second offset into said program counter when said second programmable event control register is programmed to store the sum of said first memory address plus said second offset into said program counter when second event occurs.
7. The processor of claim 6 wherein said first offset is an integral multiple of an integer and said second offset is an integral multiple of said integer.
8. The processor of claim 6 wherein said activation controller is also for:
(4.3) storing a second memory address into said program counter when said first programmable event control register is programmed to store said second memory address into said program counter when said first event occurs, and
(4.4) storing a third memory address into said program counter when said second programmable event control register is programmed to store said third memory address into said program counter when said second event occurs.
9. The processor of claim 6 wherein said activation controller is also for:
(4.3) storing the sum of a second memory address plus a third offset into said program counter when said first programmable event control register is programmed to store the sum of said second memory address plus said third offset into said program counter when said first event occurs, and
(4.4) storing the sum of said second memory address plus a fourth offset into said program counter when said second programmable event control register is programmed to store the sum of said second memory address plus said fourth offset into said program counter when said second event occurs.
10. The processor of claim 9 wherein said third offset is an integral multiple of an integer and said fourth offset is an integral multiple of said integer.
11. The processor of claim 9 wherein said activation controller is also for:
(4.3) leaving said first memory address unmodified when said first programmable event control register is programmed to leave said first memory address unmodified when said first event occurs, and
(4.4) leaving said second memory address unmodified when said second programmable event control register is programmed to leave said second memory address unmodified when said second event occurs.
12. The processor of claim 6 wherein said activation controller is also for:
(4.3) ignoring said first event when said first programmable event control register designates that said first event is to be ignored, and
(4.4) ignoring said second event when said second programmable event control register designates that said second event is to be ignored.
13. A multi-threaded processor comprising:
(1) a context controller;
(2) an activation controller; and
(3) a plurality of hardware contexts, wherein each of said hardware contexts comprises:
(3.1) a program counter that stores a first memory address.
(3.2) a first programmable event control register associated with a first event, wherein said first programmable event control register can be programmed to designate:
(3.2.1) that said first memory address is to be left unmodified when said first event occurs
(3.2.2) that the sum of a second memory address plus a first offset is to be stored in said program counter when said first event occurs; and
(3.3) a second programmable event control register associated with a second event, wherein said second programmable event control register can be programmed to designate:
(3.3.1) that said first memory address is to be left unmodified when said second event occurs
(3.3.2) that the sum of a second memory address plus a second offset is to be stored in said program counter when said second event occurs.
14. The processor of claim 13 wherein said first offset is an integral multiple of an integer and said second offset is an integral multiple of said integer.
15. The processor of claim 13 wherein said first programmable event control register can also be programmed to designate:
(3.2.3) that the sum of said first memory address plus a first offset is to be stored in said program counter when said first event occurs, and
wherein said second programmable event control register can also be programmed to designate:
(3.3.3) that the sum of said first memory address plus a first offset is to be stored in said program counter when said first event occurs.
16. The processor of claim 15 wherein said third offset is an integral multiple of an integer and said fourth offset is an integral multiple of said integer.
17. The processor of claim 13 wherein said first programmable event control register can also be programmed to designate:
(3.2.3) that said first event is to be ignored, and
wherein said second programmable event control register can also be programmed to designate:
(3.3.3) that said second event is to be ignored.