Calibrating a testing device

1. A method of calibrating automatic test equipment(ATE), comprising:

adding jitter to a test signal to produce a jittered signal;

sampling the jittered signal to produce digital values, wherein sampling is performed using an under-sampling technique that samples the jittered signal in multiple cycles, and wherein, in a current sampling cycle, sampling is performed at substantially regular offsets relative to sampling performed in a previous sampling cycle such that different parts of the jittered signal are sampled in different cycles;

generating a reconstructed jittered signal from the digital values;

determining an amount of jitter in the reconstructed jittered signal,wherein determining the amount of jitter in the reconstructed signal comprises obtaining a difference between a maximum edge time and minimum edge time in the reconstructed jittered signal;

wherein the amount of jitter in the reconstructed jittered signal includes jitter introduced by two or more hardware elements;

wherein an amount of jitter added to produce the jittered signal is predicted and an amount of jitter introduced by the two or more hardware elements is unexpected; and

calibrating the ATE based on the amount of jitter in the reconstructed jittered signal.

2. The method of claim 1 , wherein the jitter is sampled using a walking strobe clock.

3. The method of claim 1 , wherein adding jitter to the test signal comprises:

generating a periodic waveform;

changing an amplitude of the periodic waveform to produce an altered waveform;

controlling a phase shifter using the altered waveform;

applying a clock signal to the phase shifter to produce a phase-shifted signal; and

using the phase-shifted signal to generate the jittered signal;

wherein the phase shifter shifts a phase of the clock signal by an amount that corresponds to an amplitude of the altered waveform.

4. The method of claim 3 , wherein the method comprises using a clock generator to apply the clock signal and using an output of a digital-to-analog controller (DAC) to change the amplitude of the periodic waveform; and

wherein the method further comprises:

obtaining an amount of jitter in reconstructed jittered signals for combinations of a DAC input value, clock generator frequency, and jitter frequency;

wherein calibrating is based, at least in part, on resulting measurements of the amount of jitter in the reconstructed jittered signals for the combinations.

5. The method of claim 4 , wherein calibrating comprises using at least one of interpolation, extrapolation, and curve fitting to obtain amounts of jitter.

6. The method of claim 5 , wherein calibrating comprises storing, on the ATE, data corresponding to obtained amounts of jitter for the combinations of DAC input value, clock generator frequency, and jitter frequency, the data being usable to obtain a specified amount of jitter during testing of a device using the ATE.

7. Automatic test equipment (ATE) comprising:

circuitry to add jitter to a test signal to produce a jittered signal;

a clock generator to produce a clock signal;

a comparator to sample the jittered signal in accordance with the clock signal, and, as a result of sampling, to output digital values, wherein sampling is performed using an under-sampling technique that samples the jittered signal in multiple cycles, and wherein, in a current sampling cycle, sampling is performed at substantially regular offsets relative to a previous sampling cycle such that different parts of the jittered signal are sampled in different cycles; and

one or more processing devices to generate a reconstructed jittered signal from the digital values, to determine an amount of jitter in the reconstructed jittered signal, and to calibrate the ATE based on the amount of jitter in the reconstructed jittered signal;

wherein determining the amount of jitter in the reconstructed signal comprises obtaining a difference between a maximum edge time and minimum edge time in the reconstructed jittered signal;

wherein the amount of jitter in the reconstructed jittered signal includes jitter introduced by two or more hardware elements; and

wherein an amount of jitter added to produce the jittered signal is predicted and an amount of jitter introduced by the two or more hardware elements is unexpected.

8. The ATE of claim 7 , wherein the clock generator is configured to generate a walking strobe clock, the walking strobe clock having a frequency that is used for sampling.

9. The ATE of claim 7 , wherein the circuitry comprises:

a direct digital synthesizer to generate a periodic waveform;

a digital-to-analog controller (DAC) to provide data for controlling an amplitude of the periodic waveform;

a variable gain amplifier to control the amplitude of the periodic waveform in accordance with the data to produce an altered waveform;

a phase shifter that is controllable using the altered waveform;

a signal generator to apply a clock signal to the phase shifter to produce a phase-shifted signal; and

an edge generator to produce the jittered signal based on the phase-shifted signal;

wherein the phase shifter is configured to shift a phase of the clock signal by an amount that corresponds to an amplitude of the altered waveform.

10. The ATE of claim 8 , further comprising memory to store data corresponding to an amount of jitter added to the test signal, the data being usable to obtain a requested amount of jitter during testing of a device using the ATE.

11. The ATE of claim 9 , wherein calibrating the ATE comprises:

obtaining an amount of jitter in reconstructed jittered signals for different combinations of a DAC input value, signal generator frequency, and jitter frequency.

12. The ATE of claim 11 , wherein the one or more processing devices are configured to determine the DAC input value and using at least one of interpolation, extrapolation, and curve fitting to obtain jitter amounts from the reconstructed jittered signals.

13. One or more machine-readable media comprising instructions that are executable by one or more processing devices to calibrate automatic test equipment (ATE), the instructions for causing the one or more processing devices to:

generate a reconstructed jittered signal from digital values that were sampled from a jittered signal using a clock signal, the jittered signal. comprising a test signal to which an amount of jitter has been added;

wherein the digital values were sampled using an under-sampling technique that samples the jittered signal in multiple cycles, and wherein, in a current sampling cycle, sampling is performed at substantially regular offsets relative to a previous sampling cycle such that different parts of the jittered signal are sampled in different cycles;

determine an amount of jitter in the reconstructed jittered signal wherein determining the amount of jitter in the reconstructed signal comprises obtaining a difference between a maximum edge time and minimum edge time in the reconstructed jittered signal;

wherein the amount of jitter in the reconstructed jittered signal includes jitter introduced by two or more hardware elements;

wherein an amount of jitter added t produce the jittered signal is predicted and an amount of jitter introduced by the two or more hardware elements is unexpected; and

calibrate the ATE based on the amount of jitter in the reconstructed jittered signal.

14. The one or more machine-readable media of claim 13 , wherein the jitter is sampled using a walking strobe clock; and

wherein the one or more machine-readable media further comprises instructions that are executable to cause the one or more processing devices to store, on the ATE, data corresponding to an amount of jitter added to the test signal, the data being usable to obtain a predefined amount of jitter during testing of a device using the ATE.

15. The one or more machine-readable media of claim 14 , wherein calibrating the ATE comprises calibrating the ATE for one or more different combinations of conditions that produce jitter.

16. Circuitry comprising:

a phase shifter to add jitter to a test signal to produce a jittered signal;

a circuit to sample the jittered signal using a walking strobe clock to thereby produce digital values, corresponding to jitter introduced into the jittered signal;

wherein sampling is performed using an wider-sampling technique that samples the jittered signal in multiple cycles, and wherein, in a current sampling cycle, sampling is performed at substantially regular offsets relative to a previous sampling cycle such that different parts of the jittered signal are sampled in different cycles; and

one or more processing devices to store, in memory on a testing device, data indicative of an amount of jitter to be added to an output signal to produce a desired amount of jitter in the output signal, wherein the data is based on the digital values;

wherein the data indicative of an amount of jitter is determined based on a difference between a maximum edge time and minimum edge time in a reconstructed jittered signal;

wherein the amount of jitter in the reconstructed jittered signal includes jitter introduced by two or more hardware elements; and

wherein an amount of jitter added to produce the jittered signal is predicted and an amount of jitter introduced by the two or more hardware elements is unexpected.

17. The circuitry of claim 16 , further comprising a clock generator to generate the walking strobe clock, the walking strobe clock having a frequency that is used for sampling.

18. A method of calibrating automatic test equipment (ATE), comprising:

adding jitter to a test signal to produce a jittered signal;

sampling the jittered signal to produce digital values;

generating a reconstructed jittered signal from the digital values;

determining an amount of jitter in the reconstructed jittered signal; and

calibrating the ATE based on the amount of jitter in the reconstructed jittered signal wherein adding jitter to the test signal comprises:

generating a periodic waveform;

changing an amplitude of the periodic waveform to produce an altered waveform;

controlling a phase shifter using the altered waveform;

applying a clock signal to the phase shifter to produce a phase-shifted signal; and

using the phase-shifted signal to generate the jittered signal;

wherein the phase shifter shifts a phase of the clock signal by an amount that corresponds to an amplitude of the altered waveform;

wherein the method further comprises:

using a clock generator to apply the clock signal and using an output of a digital-to-analog controller (DAC) to change the amplitude of the periodic waveform;

obtaining amounts of jitter in reconstructed jittered signals for combinations of a DAC input value, clock generator frequency, and jitter frequency; and

wherein calibrating is based, at least in part, on resulting measurements of the amount of jitter in the reconstructed jittered signals for the combinations.

19. The method of claim 18 , wherein calibrating comprises using at least one of interpolation, extrapolation, and curve fitting to obtain amounts of jitter.

20. The method of claim 18 , wherein the jitter is sampled using a walking strobe clock, the walking strobe clock having a frequency that is different from a frequency of the jittered signal.

21. The method of claim 19 , wherein calibrating comprises storing, on the ATE, data corresponding to obtained amounts of jitter for the combinations of DAC input value, clock generator frequency, and jitter frequency, the data being usable to obtain a specified amount of jitter during testing of a device using the ATE.

22. Automatic test equipment (ATE) comprising:

circuitry to add jitter to a test signal to produce a jittered signal;

a clock generator to produce a clock signal;

a comparator to sample the jittered signal in accordance with the clock signal, and, as a result of sampling, to output digital values; and

one or more processing devices to generate a reconstructed jittered signal from the digital values, to determine an amount of jitter in the reconstructed jittered signal, and to calibrate the ATE based on the amount of jitter in the reconstructed jittered signal;

wherein the circuitry comprises:

a direct digital synthesizer to generate a periodic waveform;

a digital-to-analog controller (DAC) to provide data for controlling an amplitude of the periodic waveform;

a variable gain amplifier to control the amplitude of the periodic waveform in accordance with the data to produce an altered waveform;

a phase shifter that is controllable using the altered waveform;

a signal generator to apply a clock signal to the phase shifter to produce a phase-shifted signal; and

an edge generator to produce the jittered signal based on the phase-shifted signal;

wherein the phase shifter is configured to shift a phase of the clock signal by an amount that corresponds to an amplitude of the altered waveform.

23. The ATE of claim 22 , wherein calibrating the ATE comprises:

obtaining an amount of jitter in reconstructed jittered signals for different combinations of a DAC input value, signal generator frequency, and jitter frequency.

24. The ATE of claim 22 , wherein the clock generator is configured to generate a walking strobe clock, the walking strobe clock having a frequency that is different from a frequency of the jittered signal.

25. The ATE of claim 23 , wherein the one or more processing devices are configured to determine the DAC input value and using at least one of interpolation, extrapolation, and curve fitting to obtain jitter amounts from the reconstructed jittered signals.