Masked spacer etching for imagers
The invention relates to a dual masked spacer etch for improved dark current performance in imagers. After deposition of spacer material such as oxide, N-channel regions are first opened for N + source/drain implant and P-channel regions are then opened for P + source/drain implant. Prior to the N + source/drain implant, the wafer receives a patterned first spacer etch. During this first spacer etch, the photosensor region is covered with resist. Prior to the P + source/drain implant, a masked second spacer etch is performed. Again the photosensor region is protected with photoresist. In such a manner, spacers are formed on the gates of both the N-channel and P-channel transistors but in the photodiode region the spacer insulator remains.
1. An imaging array comprising:
at least one pixel, wherein the pixel is part of a CCD imager, comprising:
a photosensitive region;
a gate structure;
a first insulating layer formed over substantially all of the photosensitive region;
an insulating spacer formed from the first insulating layer and on at least one side of the gate structure; and
a second insulating layer formed over said first insulating layer, said gate structure, and said spacer.
2. An integrated circuit with an imaging array comprising:
at least one pixel, wherein the pixel is part of a CCD imager, comprising:
a photosensitive region;
a first gate structure;
a first insulating layer formed over the photosensitive region;
a first insulating spacer formed from the first insulating layer and on at least one side of the first gate structure;
a peripheral circuit, said peripheral circuit having at least one transistor with a second gate structure and a second insulating spacer formed from the first insulating layer and on at least one side of the second gate structure; and
a second insulating layer formed over said first insulating layer, said first gate structure, and said first insulating spacer.
3. The integrated circuit of claim 2 , wherein said second gate structure is a source follower gate.
4. The integrated circuit of claim 2 , wherein said second gate structure is a reset gate.
5. An imaging device comprising:
a semiconductor substrate; and
a pixel array, said pixel array comprising:
at least one photosensor, said photosensor covered by a continuous layer of spacer material;
at least one N-channel transistor, wherein at least one spacer formed from said spacer material is along at least one side of at least one of each said N-channel transistor's gate;
at least one of an N-channel transistor or a P-channel transistor outside said pixel array, wherein spacers formed from said spacer material are along at least one side of at least one of either said P-channel or N-channel transistor's gate; and
a translucent or transparent insulating layer formed over said imaging device.
6. The imaging device of claim 5 , wherein said insulating layer is selected from the group consisting of SiO 2 , BPSU, TEOS, BPSG, PSG, BSG, and SOG.
7. The imaging device of claim 6 , wherein electrical contacts are formed through said insulating layer.
8. An image pixel array in a CMOS imaging device, comprising:
at least one photosensor, said photosensor substantially covered by a continuous layer of spacer material;
at least one N-channel transistor having a gate and, along at least one side of the gate, a spacer formed of said spacer material; and
an insulating layer formed over said photosensor, said gate, and spacer material,
wherein each pixel of said pixel array comprises a pinned photodiode for performing photoelectric conversion.
9. The image pixel array of claim 8 , wherein said spacer material comprises at least one of an oxide, nitride, oxide/nitride, and metal oxide.
10. The image pixel array of claim 8 , wherein said pixel array comprises about 0.1 megapixels to about 20 megapixels.
11. The imaging array of claim 8 , wherein said gate is a transfer gate.
12. The imaging array of claim 8 , wherein said gate is a reset gate.
13. The imaging array of claim 8 , wherein said gate is a row select gate.
14. The imaging array of claim 8 , wherein said gate is a source follower gate.
15. An imager system, comprising:
a processor; and
an imaging device connected to provide signals to said processor, said imaging device comprising:
a semiconductor substrate; and
a pixel array, said pixel array comprising:
at least one photosensor, said photosensor covered by a continuous layer of spacer material;
at least one N-channel transistor, wherein at least one spacer formed from said spacer material is along at least one side of at least one of each said N-channel transistor's gate; and
at least one N-channel or P-channel transistor outside said pixel array, wherein at least one spacer formed from said spacer material is along at least one side of at least one of each said N-channel and P-channel transistor's gate; and
a translucent or transparent insulating layer formed over said imaging device.
16. The imager system of claim 15 , wherein said spacer material comprises at least one of an oxide, nitride, oxide/nitride, and metal oxide.
17. The imager system of claim 15 , wherein said insulating layer is selected from the group consisting of SiO 2 , BPSU, TEOS, BPSG, PSG, BSG, and SOG.