Memory device having latch for charging or discharging data input/output line
View Patent ↗A semiconductor memory device of the claimed invention, having an active state for performing a read or write operation and an inactive state except for the active state includes a data input/output (I/O) line; a pull-up latch unit for pulling-up the data I/O line when the semiconductor memory device is in the inactive state; a pull-down latch unit for pulling-down the data I/O line when the semiconductor memory device is in the inactive state; and a selection unit for selectively driving one of the pull-up latch unit and the pull-down latch unit.
1. A semiconductor memory device having an active state for performing a read or write operation and an inactive state, comprising:
a data input/output (I/O) line;
a latch unit directly connected to the data I/O line, for preventing the data I/O line from floating; and
a charging unit for controlling the latch unit to charge the data I/O line when the semiconductor memory device is in the inactive states,
wherein the inactive state comprises a standby mode and a self-refresh mode, and wherein the charging unit determines a logic level of an output signal of the latch unit based on a charging signal generated by combining a clock enable signal denoting an enable state of a clock signal of the semiconductor memory device and a row address strobe (RAS) idle signal transitioning the standby mode.
2. The semiconductor memory device as recited in claim 1 , wherein the charging unit determines a logic level of an output signal of the latch unit based on a charging signal generated by using a clock enable signal denoting an enable state of a clock signal of the semiconductor memory device.
3. The semiconductor memory device as recited in claim 1 , wherein the charging unit determines a logic level of an output signal of the latch unit based on a charging signal generated by using a self-refresh signal transitioning the self-refresh mode.
4. A semiconductor memory device having an active state for performing a read or write operation and an inactive state, comprising:
a data input/output (I/O) line;
a latch unit for preventing the data I/O line from floating; and
a discharging unit for controlling the latch unit to discharge the data I/O line when the semiconductor memory device is in the inactive state,
wherein the inactive state comprises a standby mode and a self-refresh mode, and wherein the discharging unit determines a logic level of an output signal of the latch unit based on a discharging signal generated by combining a clock enable signal denoting an enable state of a clock signal of the semiconductor memory device and a row address strobe (RAS) idle signal transitioning the standby mode.
5. The semiconductor memory device as recited in claim 4 , wherein the discharging unit determines a logic level of an output signal of the latch unit based on a discharging signal generated by using a clock enable signal denoting an enable state of a clock signal of the semiconductor memory device.
6. The semiconductor memory device as recited in claim 4 , wherein the discharging unit determines a logic level of an output signal of the latch unit based on a discharging signal generated by using a self-refresh signal transitioning the self-refresh mode.