High speed, out-of-band differential pin driver
View Patent ↗A driver block for a differential pin driver that supports out-of-band signaling. The driver block includes a main enable switch that is controlled by a high speed driver inhibit (DINH) signal. The main enable switch controls coupling between a main current source and a differential pin driver output stage. The main enable switch is coupled in series with an output select switch that selects between a positive output and a negative output. The driver block also includes a positive enable switch for controlling coupling between the positive output and a positive level shifter that shifts voltages of the positive output. The driver block also includes a negative enable switch for controlling coupling between the negative output and a negative level shifter that shifts voltages of the negative output.
1. A differential pin driver, comprising:
a class-A differential pin driver output stage comprising a positive output and a negative output selectable by a high speed signal output select (DHI) signal controlling an output select switch;
a driver block for providing out-of-band signaling that is controlled by a high speed driver inhibit signal (DINH) that controls a main enable switch controlling coupling between a main current source and said positive and negative outputs, wherein said main enable switch is coupled in series with said output select switch; and
a level shifter block for level shifting voltages of said positive output and said negative output.
2. The differential pin driver of claim 1 , wherein said class-A differential pin driver output stage further comprises:
wherein said output select switch selectably controls coupling to said positive output and said negative output; and
a high reference voltage coupled to said positive output through a first resistor, and coupled to said negative output through a second resistor.
3. The differential pin driver of claim 2 , wherein said first resistor and second resistor are identical.
4. The differential pin driver of claim 1 , further comprising a voltage input for adjusting current output from said main current source.
5. The differential pin driver of claim 1 , wherein said driver block comprises:
said main enable switch coupled in series between said output switch and said main current source;
a positive enable switch coupled to said positive output and said level shifter block, wherein said positive enable switch is controlled by a positive enable signal; and
a negative enable switch coupled to said negative output and said level shifter block, wherein said negative enable switch is controlled by a negative enable signal.
6. The differential pin driver of claim 1 , wherein said level shifter block comprises:
a controllable positive output current source coupled to said positive output and said positive enable switch; and
a controllable negative output current source coupled to said negative output and said negative enable switch.
7. The differential pin driver of claim 1 , wherein said driver block further comprises:
a plurality of logic gates for controlling said main enable switch, said positive enable switch, and said negative enable switch, wherein said plurality of logic gates accepts a plurality of inputs including said DINH signal, and a plurality of input modes.
8. The differential pin driver of claim 1 , wherein said positive output and negative output provides a multi-level differential signal of up to four levels.
9. A differential pin driver, comprising:
a class-A differential pin driver output stage comprising a positive output and a negative output selectable by a high speed output select signal controlling an output select switch;
a positive level shifter for level shifting a voltage of said positive output;
a negative level shifter for level shifting a voltage of said negative output; and
a driver block for providing out of band signaling controlled by a high speed driver inhibit (DINH) signal.
10. The differential pin driver of claim 9 , wherein said driver block comprises:
a main enable switch controlled by a main enable signal, wherein said main enable switch is coupled in series with said output select switch for controlling coupling between a main current source and said class-A differential pin driver output stage;
a positive enable switch for controlling coupling between said positive output and said positive level shifter, wherein said positive enable switch is controlled by a positive enable signal; and
a negative enable switch for controlling coupling between said negative output and said negative level shifter, wherein said negative enable switch is controlled by a negative enable signal.
11. The differential pin driver of claim 9 , wherein said driver block further comprises:
a plurality of logic gates for controlling said main enable switch, said positive enable switch, and said negative enable switch, wherein said plurality of logic gates accepts a plurality of inputs including said DINH signal and a plurality of input modes.
12. The differential pin driver of claim 9 , wherein said positive level shifter comprises:
a controllable positive output current source coupled to said positive output.
13. The differential pin driver of claim 9 , wherein said negative level shifter comprises:
a controllable negative output current source coupled to said negative output.
14. A driver block for a differential pin driver, comprising:
a main enable switch controlled by a high speed driver inhibit (DINH) signal for controlling coupling between a main current source and a differential pin driver output stage, wherein said main enable switch is coupled in series to an output select switch for selecting between a positive output and a negative output;
a positive enable switch for controlling coupling between said positive output and a positive level shifter that shifts voltages of said positive output, wherein said positive enable switch is controlled by a positive enable signal; and
a negative enable switch for controlling coupling between said negative output and a negative level shifter that shifts voltages of said negative output, wherein said negative enable switch is controlled by a negative enable signal.
15. The driver block of claim 14 , wherein said driver block drives a class-A differential pin driver comprising:
said differential pin driver output stage comprising said positive output and said negative output;
said main current source, wherein said output select switch is coupled to said main current source, said positive output, and said negative output; and
a high reference voltage coupled to said positive output through a first resistor, and coupled to said negative output through a second resistor.
16. The driver block of claim 15 , wherein said first and second resistors are identical.
17. The driver block of claim 14 , further comprising:
a plurality of logic gates for controlling said main enable switch, said positive enable switch, and said negative enable switch, wherein said plurality of logic gates accepts a plurality of inputs including said DINH signal and a plurality of input modes.
18. The driver block of claim 14 , wherein said output select switch is controlled by a high speed output select signal (DHI).
19. The driver block of claim 14 , wherein said positive output and negative output provides a multi-level differential signal.
20. The driver block of claim 14 , wherein said positive level shifter comprises a controllable positive output current source coupled to said positive output; and wherein said negative level shifter comprises a controllable negative output current source coupled to said negative output.