Method for fabricating semiconductor device having recess gate
View Patent ↗A method for fabricating a semiconductor device having a recess gate includes forming a hard mask pattern on a substrate, etching the substrate using the hard mask pattern as an etch barrier to form a recess pattern, forming a passivation layer protecting surfaces of the recess pattern, etching a bottom surface of the recess pattern while protecting sidewalls of the recess pattern, performing an isotropic etching process onto a bottom portion of the recess pattern, and forming a gate pattern partially buried into the recess pattern after the isotropic etching process is performed.
1. A method for fabricating a semiconductor device, the method comprising:
forming a hard mask pattern on a substrate;
etching the substrate using the hard mask pattern as an etch barrier to form a first recess;
forming a spacer layer over the resultant substrate structure after etching the substrate;
etching the substrate below the first recess using the spacer layer and the hard mask pattern as an etch barrier to form a second recess;
performing an isotropic etching process to transform the second recess into a round shape having a larger width than the first recess;
removing the spacer layer after performing the isotropic etching process; and
forming a gate pattern partially buried into the first and second recess after the isotropic etching process is performed.
2. The method of claim 1 , wherein the hard mask pattern comprises a conductive layer containing silicon.
3. The method of claim 2 , wherein the hard mask pattern includes a stacked structure of oxide and polysilicon.
4. The method of claim 1 , wherein the forming of the spacer layer comprises oxidizing surfaces of the first recess and the hard mask pattern.
5. The method of claim 4 , wherein the oxidizing surfaces of the first recess and the hard mask pattern comprises flowing oxygen (O 2 ).
6. The method of claim 5 , wherein the flowing of O 2 comprises flowing O 2 in a furnace.
7. The method of claim 6 , wherein the furnace is maintained at a temperature ranging from approximately 800° C. to approximately 900° C.
8. The method of claim 4 , wherein the spacer layer is formed to a thickness ranging from approximately 40 Å to approximately 80 Å.
9. The method of claim 1 , wherein the forming of the first recess comprises using a plasma including hydrogen bromide (HBr) and chlorine (Cl 2 ).
10. The method of claim 9 , wherein the first recess is formed to a depth ranging from approximately 400 Å to approximately 500 Å.
11. The method of claim 1 , wherein the etching of the substrate below the first recess comprises using a plasma including HBr and Cl 2 .
12. The method of claim 1 , wherein the performing of the isotropic etching process to transform the second recess comprises performing the isotropic etching process at a dry etch apparatus attached with a microwave generator.
13. The method of claim 12 , wherein the isotropic etching process is performed under a condition that allows a selective etching of the second recess at the dry etch apparatus attached with the microwave generator.
14. The method of claim 13 , wherein the condition comprises using a fluorocarbon-based gas.
15. The method of claim 14 , wherein the fluorocarbon-based gas includes carbon tetrafluoride (CF 4 ) gas.
16. The method of claim 15 , wherein the CF 4 gas flows at a rate ranging from approximately 100 sccm to approximately 200 sccm.
17. The method of claim 1 , further comprising, after the performing of the isotropic etching process to transform the second recess:
removing the spacer layer and the hard mask pattern; and
rounding top corners of the first and second recess to form a flask-shaped recess pattern.
18. The method of claim 17 , wherein the rounding of the top corners comprises using a gas including CF 4 and O 2 .