Method of manufacturing semiconductor device having conductive thin films
View Patent ↗In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5 , for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6 . The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.
1. A method of manufacturing a gate electrode, comprising the steps of:
forming first amorphous silicon on a gate insulating film;
crystallizing said first amorphous silicon to form a first polycrystalline silicon;
forming a second amorphous silicon on said first polycrystalline silicon; and
crystallizing said second amorphous silicon to form a second polycrystalline silicon.
2. A method of manufacturing a gate electrode according to claim 1 , wherein said gate insulating film is silicon oxide film.
3. A method of manufacturing a gate electrode according to claim 1 , wherein thickness of said first polycrystalline silicon and said second polycrystalline silicon are at most 100 nm.
4. A method of manufacturing a gate electrode according to claim 1 , wherein thickness of said first amorphous silicon and said second amorphous silicon are at most 100 nm.
5. A method of manufacturing a gate electrode according to claim 1 , wherein thickness of said first polycrystalline silicon and said second polycrystalline silicon are sufficiently small such that a fail event in the gate electrode is prevented.
6. A method of manufacturing a gate electrode, comprising the steps of:
forming first amorphous silicon on an oxide film;
crystallizing said first amorphous silicon to form a first polycrystalline silicon;
forming a second amorphous silicon on said first polycrystalline silicon; and
crystallizing said second amorphous silicon to form a second polycrystalline silicon.
7. A method of manufacturing a gate electrode according to claim 6 , wherein said oxide film is silicon oxide film.
8. A method of manufacturing a gate electrode according to claim 6 , wherein thickness of said first polycrystalline silicon and said second polycrystalline silicon are at most 100 nm.
9. A method of manufacturing a gate electrode according to claim 6 , wherein thickness of said first amorphous silicon and said second amorphous silicon are at most 100 nm.