Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
View Patent ↗A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.
1. A method for reconfiguring cache memory, comprising:
analyzing one or more characteristics of an execution entity accessing a cache memory, said one or more characteristics of an execution entity including at least size of data structure used by the execution entity, expected reference pattern of the execution entity, and heat generated by the execution entity, said analyzing including at least reading temperature data associated with the execution entity to determine amount of heat generated by the execution entity, said analyzing being performed on-line while the execution entity is being run; and
reconfiguring the cache memory dynamically based on the one or more characteristics analyzed, the step of reconfiguring including modifying associativity of the cache memory, modifying amount of the cache memory available to store data, changing coherence granularity of the cache memory, or modifying line size of the cache memory, or combination thereof,
said step of reconfiguring including at least:
changing number of masked bits for mapping into the cache memory to modify cache memory associativity;
dividing a cache line in the cache memory into a plurality of sectors, and accessing data of the cache line by one or more sectors;
instructing hardware as to which memory region should be cached by sectors and which memory region should be cached by entire cache lines; and
associating an access bit with each sector of a cache line, and setting an access bit to true if a processing element uses data of a sector associated with the access bit, said step of associating including at least associating an access bit with each sector of a cache line in level-1 cache; and
associating a granularity bit with each sector of a cache line in level-2 cache, the granularity bit for indicating whether a sector should be cached when one or more other sectors in the cache line in level-2 are cached.