Nonvolatile ferroelectric memory device and method thereof

1. A nonvolatile ferroelectric memory device having a plurality of ferroelectric memory cells, the ferroelectric memory cells comprising:

a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the floating channel layer corresponding to the bit of datum stored in the first double gate cell; and

a second double gate cell selectively turned on by a potential on a selection line to supply a potential of a sense line to the floating channel layer of the first double gate cell to control read and write operations of the first double gate cell.

2. A device according to claim 1 , wherein the first double gate cell further comprises:

a bottom word line;

an insulating layer formed over the bottom word line, wherein the floating channel layer comprises a p-type channel region formed over the insulating layer, and the ferroelectric layer is formed over the floating channel layer;

a top word line formed over the ferroelectric layer;

a p-type drain region; and

a p-type source region, wherein the p-type drain region and the p-type source region are on respective sides of the floating channel layer.

3. A device according to claim 1 , wherein the floating channel layer comprises one of a carbon nano tube, silicon, germanium, or an organic semiconductor.

4. The nonvolatile ferroelectric memory device according to claim 1 , wherein

the floating channel layer is operable between first and second resistance conditions, the first resistance condition having a lower resistance than the second resistance condition, and

the floating channel layer is in the first resistance condition when positive charges are induced therein by a polarization of the ferroelectric layer.

5. The nonvolatile ferroelectric memory device according to claim 1 , wherein

the floating channel layer is operable between first and second resistance conditions, the first resistance condition having a lower resistance than the second resistance condition, and

the floating channel layer is in the second resistance condition when negative charges are induced therein by a polarization of the ferroelectric layer.

6. A nonvolatile ferroelectric memory device having a plurality of ferroelectric memory cells, the ferroelectric memory cells comprising:

a double gate cell for storing a bit of datum, the double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the channel layer corresponding to the bit of datum stored in the first double gate cell; and

a switch unit selectively turned on by a potential on a selection line to supply a potential of a sense line to the floating channel layer of the double gate cell so as to control read and write operations of the double gate cell.

7. The nonvolatile ferroelectric memory device according to claim 6 , wherein the double gate cell comprises:

a bottom word line;

an insulating layer formed over the bottom word line, wherein the floating channel layer comprises a p-type channel region formed over the insulating layer, and the ferroelectric layer is formed over the floating channel layer;

a top word line formed over the ferroelectric layer;

a p-type drain region; and

a p-type source region, wherein the p-type drain region and the p-type source region are formed on respective sides of the floating channel layer.

8. The nonvolatile ferroelectric memory device according to claim 7 , wherein the floating channel layer comprises one of a carbon nano tube, silicon, germanium, or an organic semiconductor.

9. The nonvolatile ferroelectric memory device according to claim 6 , wherein

the floating channel layer is operable between first and second resistance conditions, the first resistance condition having a lower resistance than the second resistance condition, and

the floating channel layer is in the first resistance condition when positive charges are induced therein by a polarization of the ferroelectric layer.

10. The nonvolatile ferroelectric memory device according to claim 6 , wherein

the floating channel layer is operable between first and second resistance conditions, the first resistance condition having a lower resistance than the second resistance condition, and

the floating channel layer is in the second resistance condition when negative charges are induced therein by a polarization of the ferroelectric layer.

11. The nonvolatile ferroelectric memory device according to claim 6 , wherein the switch comprises an MOS transistor.

12. A nonvolatile ferroelectric memory device having at least one ferroelectric memory cell array, the ferroelectric memory cell array comprising:

a plurality of top word lines;

a plurality of bottom word lines;

a plurality of selection lines;

a plurality of sense lines;

a plurality of bit lines;

a plurality of sense amplifiers respectively connected to the plurality of bit lines; and

a plurality of ferroelectric memory cells connected to the top word lines, the bottom word lines, the selection lines, the sense lines, and the bit lines,

wherein each of the plurality of ferroelectric memory cells comprises:

a first double gate cell for storing a bit of datum, the first double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the channel layer corresponding to the bit of datum stored in the first double gate cell; and

a second double gate cell selectively turned on by a potential on a corresponding one of the selection lines to selectively supply a potential of a corresponding one of the sense lines to the first double gate cell so as to control read and write operations of the first double gate cell.

13. The nonvolatile ferroelectric memory device according to claim 12 , wherein the first double gate cell further comprises:

an insulating layer formed over a corresponding one of the bottom word lines, wherein the floating channel layer comprises a p-type channel region formed over the insulating layer, the ferroelectric layer is formed over the floating channel layer, and a corresponding one of the top word lines is formed over the ferroelectric layer;

a p-type drain region; and

a p-type source region, wherein the p-type drain region and the p-type source region are formed on respective sides of the floating channel layer.

14. The nonvolatile ferroelectric memory device according to claim 12 , wherein the floating channel layer comprises one of a carbon nano tube, silicon, germanium, or an organic semiconductor.

15. The nonvolatile ferroelectric memory device according to claim 12 , wherein

the floating channel layer is operable between first and second resistance conditions, the first resistance condition having a lower resistance than the second resistance condition, and

the floating channel layer is in the first resistance condition when positive charges are induced therein by a polarization of the ferroelectric layer.

16. The nonvolatile ferroelectric memory device according to claim 12 , wherein

the floating channel layer is operable between first and second resistance conditions, the first resistance condition having a lower resistance than the second resistance condition, and

the floating channel layer is in the second resistance condition when negative charges are induced therein by a polarization of the ferroelectric layer.

17. A nonvolatile ferroelectric memory device having at least one ferroelectric memory cell array, the ferroelectric memory cell array comprising:

a plurality of top word lines;

a plurality of bottom word lines;

a plurality of selection lines;

a plurality of sense lines;

a plurality of bit lines;

a plurality of sense amplifiers respectively connected to the plurality of bit lines; and

a plurality of ferroelectric memory cells connected to the top word lines, the bottom word lines, the selection lines, the sense lines, and the bit lines,

wherein each of the plurality of ferroelectric memory cells comprises:

a double gate cell for storing a bit of datum, the double gate cell including a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the channel layer corresponding to the bit of datum stored in the first double gate cell; and

a switch unit selectively turned on by a potential on a corresponding one of the selection lines to selectively supply a potential of a corresponding one of the sense lines to the double gate cell so as to control read and write operations of the double gate cell.

18. The nonvolatile ferroelectric memory device according to claim 17 , wherein the double gate cell comprises:

an insulating layer formed over a corresponding one of the bottom word lines, wherein the floating channel layer comprises a p-type channel region formed over the insulating layer, the ferroelectric layer is formed over the floating channel layer, and a corresponding one of the top word lines is formed over the ferroelectric layer;

a p-type drain region; and

a p-type source region, wherein the p-type drain region and the p-type source region are formed on respective sides of the floating channel layer.

19. The nonvolatile ferroelectric memory device according to claim 17 , wherein the floating channel layer comprises one of a carbon nano tube, silicon, germanium, or an organic semiconductor.

20. The nonvolatile ferroelectric memory device according to claim 17 , wherein

the floating channel layer is operable between first and second resistance conditions, the first resistance condition having a lower resistance than the second resistance condition, and

the floating channel layer is in the first resistance condition when positive charges are induced therein by a polarization of the ferroelectric layer.

21. The nonvolatile ferroelectric memory device according to claim 17 , wherein

the floating channel layer is operable between first and second resistance conditions, the first resistance condition having a lower resistance than the second resistance condition, and

the floating channel layer is in the second resistance condition when negative charges are induced therein by a polarization of the ferroelectric layer.

22. A method for operating a nonvolatile ferroelectric memory device having a plurality of ferroelectric memory cells arranged in a plurality of rows and columns, each row corresponding to one of a plurality of top word lines, one of a plurality of bottom word lines, one of a plurality of selection lines, and one of a plurality of sense lines, and each column corresponding to one of a plurality of bit lines, wherein each of the plurality of ferroelectric memory cells comprises a double gate cell for storing a bit of datum and a switch unit selectively turned on by a potential on a corresponding one of the selection lines to supply a potential on a corresponding one of the sense lines to the double gate cell to control read and write operations of the double gate cell, the method comprising:

writing a bit of “1” into each of first ones of the ferroelectric memory cells by

applying a positive voltage to the corresponding selection line to turn off the corresponding switch unit,

applying a ground voltage to the corresponding bit line and the corresponding bottom word line, and

applying a negative polarization transition threshold voltage to the corresponding top word line.

23. The method according to claim 22 , wherein each of the double gate cells of the ferroelectric memory cells includes a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the channel layer corresponding to a bit of datum stored in the first double gate cell, and

wherein writing a bit of “1” into each of the first ones of the ferroelectric memory cells comprises setting a polarization of the ferroelectric layers of the double gate cells of the first ones of the ferroelectric memory cells to induce positive charges in the corresponding floating channel layers.

24. The method according to claim 22 , further comprising:

maintaining data stored in second ones of the ferroelectric memory cells by

applying a positive voltage to the corresponding selection lines,

applying a ground voltage to the corresponding bottom word lines,

applying a positive polarization transition threshold voltage to the corresponding top word lines, and

applying a voltage having a level of half that of the positive polarization transition threshold voltage to the corresponding bit lines.

25. The method according to claim 24 , further comprising:

writing a bit of “0” into each of third ones of the ferroelectric memory cells by applying a positive voltage to the corresponding selection lines,

applying a ground voltage to the corresponding bottom word lines, applying a positive polarization transition threshold voltage to the corresponding top word lines, and

applying the ground voltage to the corresponding bit lines.

26. The method according to claim 25 , wherein each of the double gate cells of the ferroelectric memory cells includes a ferroelectric layer and a floating channel layer, wherein a polarity state of the ferroelectric layer affects a resistance of the floating channel layer, the resistance of the channel layer corresponding to the bit of datum stored in the first double gate cell, and

wherein writing a bit of “0” into each of the third ones of the ferroelectric memory cells comprises setting a polarization of the ferroelectric layers of the double gate cells of the third ones of the ferroelectric memory cells to induce negative charges in the corresponding floating channel layers.

27. The method according to claim 25 , wherein maintaining data stored in the second ones of the ferroelectric memory cells and writing a bit of “0” into each of the third ones of the ferroelectric memory cells are performed simultaneously.

28. The method according to claim 22 , further comprising:

reading data stored in selected ones of the ferroelectric memory cells by

applying a ground voltage to the corresponding selection lines and the corresponding top word lines,

applying a positive read voltage to the corresponding bottom word lines, and

applying a sense voltage to the corresponding bit lines.

29. The method according to claim 22 , wherein the switch unit comprises another double gate cell.

30. The method according to claim 22 , wherein the switch unit comprises an MOS transistor.