Modular design of multiport memory bitcells
The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.
1. A system for creating a modular port-scalable memory bitcell, the system comprising:
a basic memory storage node having at least one associated port, a first pull-down device and a second pull-down device;
a first modular port cell, having a first modular connection that is coupled to the first pull-down device, that communicates data to a memory cell;
a second modular port cell, having a second modular connection that is coupled to the second pull-down device, that communicates data to the memory cell; and
wherein the first and second modular port cells are coupled to the basic memory storage node without disturbing the general layout of the basic memory storage node.
2. The system of claim 1 wherein the first modular port cell further comprises an access device, coupled between a first wordline, a first bitline and the first pull-down device, that accesses data contained within the memory cell.
3. The system of claim 1 wherein the first modular port cell is a single-ended read port module.
4. The system of claim 3 wherein the first modular connection is coupled between the first pull-down device and a read transistor in the single-ended read port module.
5. The system of claim 1 wherein the second modular port cell is a differential write port module.
6. The system of claim 5 wherein the second modular port cell comprises:
a second access device, coupled between a second wordline, a second bitline, and the second pull-down device, that accesses or changes data within the memory cell;
a third access device, coupled the second wordline, a third bitline, and the first pull-down device, that accesses or changes data within the memory cell; and
wherein the second and third access devices differentially access or change data within the memory cell.
7. The system of claim 1 wherein all poly-gates within the memory bitcell are running in the same direction.
8. The system of claim 1 further comprising a first constant voltage line, coupled between a first bitline and a second bitline within a differential write port module, that provides a constant voltage to a write transistor within the differential write port module and reduces cross-coupling between the first bitline from the second bitline.
9. The system of claim 1 wherein an array of bitcells includes modular port-scalable memory bitcell, and there are no breaks within diffusion layers and no enclosed areas formed by the diffusion.
10. A method for designing a multiport memory bitcell, the method comprising:
defining a basic memory storage node having a first bitline that is coupled to a first pull-down device and a second bitline that is coupled to a second pull-down device;
attaching a first single-ended read port module to the basic memory storage node by coupling a third bitline to the first pull-down device;
attaching a first differential write port module to the basic memory storage node by coupling a fourth bitline to the second pull-down device, and coupling a fifth bitline to the second pull-down device and a second write transistor; and
wherein all the polysilicon segments are oriented in a first direction and all the diffusion segments are oriented in a second direction and the general layout of the basic memory storage node is undisturbed.
11. The method of claim 10 wherein the first single-ended read port module is coupled to the basic memory storage node without having to add a third pull-down device within the first single-ended read port module and the basic memory storage node.
12. The method of claim 10 wherein the first differential write port module is coupled to the basic memory storage node without having to add a third pull-down device within the first differential write port module and the basic memory storage node.
13. The method of claim 10 further comprising manufacturing a constant voltage line between a first bitline and a second bitline within the first differential write port module to reduce cross-coupling between the first and second bitlines.
14. The method of claim 10 wherein the multiport memory bitcell is a multiport SRAM bitcell.
15. The method of claim 10 wherein the first differential write port module is structured so that a second differential write port module may be directly coupled to the first single-ended read port module in order to increase the port count within the multiport memory bitcell.
16. The method of claim 10 wherein the first single-ended read port module is halved to allow symmetric insertion within the multiport memory bitcell.
17. A modular multiport memory bitcell comprising:
an N-well having a first pull-up device;
a first modular write port cell, coupled to the N-well, having a first and second bitline on which data is written to or read from the first modular write port cell;
a second modular write port cell, coupled to the N-well, having third and fourth bitlines on which data is written on or read from the second modular write port cell;
a first modular read port cell, coupled to the first modular write port cell, having a fifth bitline on which data is read from a memory cell; and
wherein the first modular read port cell, the first modular write port cell, and second modular write port cell contain independent functionality that permits modular adaptation and expansion of the modular multiport memory bitcell.
18. The multiport memory bitcell of claim 17 wherein the bitcell reads and writes data to an SRAM memory device.
19. The multiport memory bitcell of claim 17 wherein the port count on the bitcell may be modularly scaled by a designer.
20. The multiport memory bitcell of claim 17 further comprising a constant voltage metallic line located between the third and fourth bitlines to reduce cross-coupling between the third and fourth bitlines.