IP Library Granted Patent US 7,589,344
Granted Patent B2
US 7,589,344 · App. 11/490,073 · Granted Sep 15, 2009

Semiconductor device and method of producing the same

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Quick Facts
Patent No.
US 7,589,344
App. No.
11/490,073
Granted
Sep 15, 2009
Kind
B2
Abstract

In a semiconductor device, a phase change layer is formed as a side wall and is therefore reduced in volume. Even if the number of times of rewriting is small, the phase change layer is entirely used as a phase change region. Therefore, the phase change region is not increased in volume even if the number of times of rewriting is increased. Since the volume of the phase change region is not changed, an electric current level required for rewriting is constant. Thus, the semiconductor device having a memory cell capable of carrying out stable rewriting is obtained.

Claims (31)

1. A semiconductor device comprising:

a phase change layer as a memory element of a memory cell, said phase change layer is formed as a side wall inside a contact hole formed in an interlayer insulation film; and

a buried insulation film formed in a center portion of said phase change layer,

wherein said phase change layer and said buried insulation film each have first and second electrodes directly connected to both ends thereof, and

wherein said first electrode is a heater electrode for heating said phase change layer to change between the amorphous state and the crystalline state.

2. The semiconductor device according to claim 1 , wherein the buried insulation film is a nitride film.

3. The semiconductor device according to claim 1 , wherein the phase change layer in the contact hole has a ring shape, the second electrode being an upper electrode.

4. The semiconductor device according to claim 1 , wherein the phase change layer is entirely used as a phase change region even in a first rewriting operation.

5. The semiconductor device according to claim 1 , wherein the semiconductor device further comprises a first insulation film formed inside the contact hole at a position between the interlayer insulation film and the phase change layer.

6. The semiconductor device according to claim 5 , wherein the first insulation film is a nitride film.

7. The semiconductor device according to claim 1 , wherein the phase change layer is a chalcogenide layer.

8. A semiconductor device comprising:

a phase change layer as a memory element of a memory cell, said phase change layer being formed as a side wall inside a first contact hole that is formed in a first interlayer insulation film; and

a buried insulation film formed in the first contact hole, said buried insulation film being surrounded by said phase change layer,

wherein said phase change layer and said buried insulation film each have bottom surfaces at a same level, a first electrode being directly connected to the bottom surfaces of both said phase change layer and said buried insulation film, and

said phase change layer and said buried insulation film each have top surfaces at a same level, a second electrode being directly connected to the top surfaces of both said phase change layer and said buried insulation film,

wherein said first electrode is a heater electrode for heating said phase change layer to change between an amorphous state and a crystalline state.

9. The semiconductor device according to claim 8 , wherein the first electrode is formed in a second contact hole formed in a second insulation film which is disposed under the first interlayer insulation film.

10. The semiconductor device according to claim 9 , wherein a diameter of the second contact hole is larger than a diameter of the first contact hole.

11. The semiconductor device according to claim 8 , wherein the buried insulation film is a silicon nitride film.

12. The semiconductor device according to claim 8 , wherein the phase change layer in the first contact hole has a ring shape in plan view.

13. The semiconductor device according to claim 8 , wherein the phase change layer is a chalcogenide layer.

14. A semiconductor device comprising:

a phase change layer as a memory element of a memory cell, said phase change layer being formed as a side wall inside a first contact hole that is formed in a first interlayer insulation film;

a buried insulation film formed in a center portion of said phase change layer;

a first electrode directly connected to bottom surfaces of both said phase change layer and said buried insulation film; and

a second electrode directly connected to top surfaces of both said phase change layer and said buried insulation film,

wherein said first electrode is a heater electrode for heating said phase change layer to change between an amorphous state and a crystalline state.

15. The semiconductor device according to claim 14 , wherein the bottom surface of the phase change layer and the bottom surface of the buried insulation film are formed at a same level.

16. The semiconductor device according to claim 14 , wherein the top surface of the phase change layer and the bottom surface of the buried insulation film are formed at a same level.

17. The semiconductor device according to claim 14 , wherein the first electrode is formed as a plug shape being filled in a second contact hole formed in a second insulation film which is disposed under the first interlayer insulation film.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2006
From: SATO, NATSUKI
To: ELPIDA MEMORY, INC.
Reel/Frame 018119/0906 →