IP Library › Granted Patent US 7,495,465
Granted Patent B2
US 7,495,465 · App. 11/490,441 · Granted Feb 24, 2009

PVT variation detection and compensation circuit

Assignee: Freescale Semiconductor, Inc.
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Quick Facts
Patent No.
US 7,495,465
App. No.
11/490,441
Granted
Feb 24, 2009
Kind
B2
Abstract

A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.

Claims (22)

1. A compensation circuit that compensates for process, voltage and temperature (PVT) variations in an integrated circuit, the integrated circuit including a plurality of functional modules, the compensation circuit comprising:

a signal generator for generating a first signal and a second signal, wherein the signal generator includes a first comparator that receives a voltage reference signal and generates a reference current signal, an aligned process module connected to the first comparator and including a plurality of P-metal oxide semiconductor (PMOS) transistors from amongst the plurality of transistors, for generating the first signal using the reference current signal, whereby the first signal depends on aligned process corner for voltage and temperature associated with a plurality of transistors of the signal generator; and a skewed process module, coupled to the aligned process module and including at least one PMOS transistor and at least one N-metal oxide semiconductor transistor from amongst the plurality of transistors, for generating the second signal using the reference current signal, whereby the second signal depends on skewed process corners associated with the plurality of transistors of the signal generator;

a first code generator, coupled to the signal generator and receiving the first signal, for generating a first calibration code based on the first signal;

a second code generator, coupled to the signal generator and receiving the second signal, for generating a second calibration code based on the second signal; and

a mapping module coupled to the first and second code generators for providing the first and second calibration codes to the plurality of functional modules, wherein the first calibration code compensates for the Aligned Process Corner, Voltage and Temperature variations associated with the plurality of functional modules, and the second calibration code compensates for the variations associated with the skewed process corners in the plurality of functional modules.

2. The compensation circuit of claim 1 , wherein the first signal is a current signal.

3. The compensation circuit of claim 1 , wherein the second signal is a voltage signal.

4. The compensation circuit of claim 1 , wherein the first code generator comprises:

a current controlled oscillator (CCO) for generating a digital signal based on the first signal; and

a logic counter connected to the CCO for generating the first calibration code based on the digital signal.

5. The compensation circuit of claim 4 , wherein the current controlled oscillator is a ring oscillator.

6. The compensation circuit of claim 4 , wherein the first calibration code is generated by counting a number of pulses of the digital signal in a clock cycle of a reference frequency signal.

7. The compensation circuit of claim 1 , wherein the second code generator comprises at least one comparator for comparing the second signal with at least one reference voltage to generate the second calibration code.

8. A compensation circuit that compensates for process, voltage and temperature (PVT) variations in an integrated circuit, the integrated circuit including a plurality of functional modules, the compensation circuit comprising:

a signal generator for generating a first signal and a second signal, wherein the signal generator includes a first comparator that receives a voltage reference signal and generates a reference current signal, an aligned process module connected to the first comparator and including a plurality of P-metal oxide semiconductor (PMOS) transistors from amongst the plurality of transistors, for generating the first signal using the reference current signal, whereby the first signal depends on aligned process corner for voltage and temperature associated with a plurality of transistors of the signal generator; and a skewed process module, coupled to the aligned process module and including at least one PMOS transistor and at least one N-metal oxide semiconductor transistor from amongst the plurality of transistors, for generating the second signal using the reference current signal, whereby the second signal depends on skewed process corners associated with the plurality of transistors of the signal generator;

a current controlled oscillator (CCO) coupled to the signal generator for generating a digital signal based on the first signal;

a counter coupled to the CCO for generating a first calibration code based on the digital signal, wherein the first calibration code is generated by counting a number of pulses of the digital signal in a clock cycle of a reference frequency signal;

at least one second comparator coupled to the signal generator for comparing the second signal with at least one reference voltage to generate a second calibration code; and

a mapping module coupled to the counter and the second comparator for providing the first and second calibration codes to the plurality of functional modules, wherein the first calibration code compensates for the PVT variations associated with the variations in the plurality of functional modules, and the second calibration code compensates for the variations associated with the skewed process corners in the plurality of functional modules.

9. The compensation circuit of claim 8 , wherein the first signal is a current signal.

10. The compensation circuit of claim 8 , wherein the second signal is a voltage signal.

11. The compensation circuit of claim 8 , wherein the current controlled oscillator is a ring oscillator.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0793 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded May 19, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 022703/0405 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2006
From: KHAN, QADER A; WADHWA, SANJAY K; TRIPATHI, DIVYA; GK, SIDDHARTHA; MISRI, KULBHUSHAN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 018122/0281 →
Priority Claims (1)
IN 1925/2005 · Jul 22, 2005 · national
Continuity (1)
Related Publication 20070018864A1 · Jan 25, 2007