IP Library Granted Patent US 7,745,303
Granted Patent B2
US 7,745,303 · App. 11/492,823 · Granted Jun 29, 2010

Method of manufacturing a semiconductor device and the semiconductor device

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Quick Facts
Patent No.
US 7,745,303
App. No.
11/492,823
Granted
Jun 29, 2010
Kind
B2
Abstract

The present invention provides a method of manufacturing a trench with a rounded corner portion and a broadened opening. Anisotropic oxidation is carried out using a halogen oxidation method using dichloroethylene (DCE) to form an anisotropic oxide film such that the film thickness in a shoulder portion of the trench is thick and gradually decreases nearer the bottom, the anisotropic oxide film is removed, and the shoulder portion of the trench is preferentially backed off, thereby rounding the shoulder portion sufficiently to broaden the opening. Then, an insulating member is embedded in the trench. The rounded portion of the shoulder portion of the trench and vicinity thereof is used as a channel of a MOS transistor.

Claims (17)

1. A method of manufacturing a semiconductor device, comprising:

forming a first trench in a semiconductor substrate, the first trench having a first opening size;

performing oxidation with anisotropy on an inner surface of the first trench to form a sacrifice oxide film, the sacrifice oxide film having a thickness that is different locally such that a thickness of the sacrifice oxide film in a shoulder portion of the first trench is thicker than a thickness of the sacrifice oxide film in a portion other than the shoulder portion of the first trench;

removing the sacrifice oxide film to preferentially back off the shoulder portion of the trench while rounding a shape of the shoulder portion, the first trench being thereby converted into a second trench that has a second opening size that is larger than the first opening size of the first trench;

performing isotropic oxidation on an inner surface of the second trench to form an oxide film on the inner surface of the second trench, a substantial entirety of the oxide film has substantially a uniform thickness so that an opening size defined by the oxide film is smaller than the second opening size of the second trench and larger than the first opening size of the first trench; and

filling the second trench with an insulating film with an intervention of the oxide film.

2. The method as claimed in claim 1 , wherein the forming the first trench comprises:

forming on the semiconductor substrate a mask layer having an opening, the opening being defined by a side surface of the mask layer;

forming a sidewall spacer on the side surface of the mask layer defining the opening; and

etching the semiconductor substrate by using the mask layer and the sidewall spacer as the mask to form the first trench.

3. The method as claimed in claim 2 , wherein the forming the first trench further comprises removing the sidewall spacer after the etching the semiconductor substrate, and each of the performing oxidation with anisotropy, the removing the sacrifice oxide film, the performing isotropic oxidation and the filling the second trench is carried out while keeping the mask layer left.

4. The method as claimed in claim 3 , further comprising removing the mask layer after the filling the second trench.

5. The method as claimed in claim 1 , wherein the forming the first trench comprises:

forming on the semiconductor substrate a mask layer having an opening; and

etching the semiconductor substrate by using the mask layer as the mask to form the first trench; and

wherein each of the performing oxidation with anisotropy, the removing the sacrifice oxide film, the performing isotropic oxidation and the filling the second trench is carried out while keeping the mask layer left.

6. The method as claimed in claim 5 , further comprising removing the mask layer after the filling the second trench.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2006
From: YAMAMOTO, HIROHISA
To: ELPIDA MEMORY INC.
Reel/Frame 018141/0556 →